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82C50A Dataheets PDF



Part Number 82C50A
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS Asynchronous Communications Element
Datasheet 82C50A Datasheet82C50A Datasheet (PDF)

82C50A March 1997 CMOS Asynchronous Communications Element Description The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil’s advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE’s receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter c.

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82C50A March 1997 CMOS Asynchronous Communications Element Description The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil’s advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE’s receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1,1.5, or 2 stop bits. The Baud Rate Generator divides the clock by a divisor programmable from 1 to 216-1 to provide standard RS-232C baud rates when using any one of three industry standard baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use. To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals RTS, CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design. Features • • • • • • • • • • • • • • • Single Chip UART/BRG DC to 625K Baud (DC to 10MHz Clock) Crystal or External Clock Input On Chip Baud Rate Generator 1 to 65535 Divisor Generates 16X Clock Prioritized Interrupt Mode Fully TTL/CMOS Compatible Microprocessor Bus Oriented Interface 80C86/80C88 Compatible Scaled SAJI IV CMOS Process Low Power - 1mA/MHz Typical Modem Interface Line Break Generation and Detection Loopback and Echo Modes Doubled Buffered Transmitter and Receiver Single 5V Supply Ordering Information PACKAGE PDIP PLCC CERDIP TEMPERATURE RANGE (oC) 0 to +70 -40 to +85 0 to +70 -40 to +85 0 to +70 -40 to +85 -55 to +125 625K BAUD CP82C50A-5 IP82C50A-5 CS82C50A-5 IS82C50A-5 CD82C50A-5 ID82C50A-5 MD82C50A-5/B PKG. NO. E40.6 E40.6 N44.65 N44.65 F40.6 F40.6 F40.6 Functional Diagram CSO CS1 CS2 ADS A0 A1 A2 MR DISTR DISTR 12 13 14 25 28 27 26 35 22 21 LINE STATUS AND CONTROL INTERRUPT ENABLE, ID, & CONTROL MICROPROCESSOR INTERFACE 24 23 30 CSOUT DDIS INTRPT UART 10 RECEIVER DIVISOR LATCH AND BAUD RATE GENERATOR TRANSMITTER MODEM MODEM CONTROL 9 16 17 11 32 33 34 31 36 37 MODEM STATUS 38 39 SIN RCLK XTAL1 XTAL2 SOUT RTS DTR OUT1 OUT2 CTS DSR DCD RI 15 BAUDOUT DOSTR 19 DOSTR 18 D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2958.1 1 82C50A Pinouts 82C50A (PDIP, CERDIP) TOP VIEW D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2 BAUDOUT XTAL1 XTAL2 DOSTR DOSTR GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 VCC 39 RI 38 DCD 37 DSR 36 CTS 35 MR 34 OUT1 33 DTR 32 RTS 31 OUT2 30 INTRPT 29 NC 28 A0 27 A1 26 A2 25 ADS 24 CSOUT 23 DDIS 22 DISTR 21 DISTR 82C50A (PLCC) TOP VIEW DCD DSR CTS VCC NC D4 D3 D2 D1 D0 RI 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D5 D6 D7 RCLK SIN NC 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MR OUT1 DTR RTS OUT2 NC SOUT CS0 CS1 CS2 BAUDOUT INTRP NC A0 A1 A2 DOSTR DOSTR CSOUT XTAL1 XTAL2 DISTR DISTR DDIS GND 2 ADS NC 82C50A Pin Description SYMBOL DISTR, DISTR PIN NUMBER 22 21 TYPE I I ACTIVE LEVEL H L DESCRIPTION DATA IN STROBE, DATA IN STROBE: DISTR, DISTR are read inputs which cause the 82C50A to output data to the data bus (D0-D7). The data output depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DISTR, DISTR inputs. Only an active DISTR or DISTR, not both, is used to receive data from the 82C50A during a read operation. If DISTR is used as the read input, DlSTR should be tied high. If DISTR is used as the active read input, DISTR should be tied low. DOSTR, DOSTR 19 18 I I H L DATA OUT STROBE, DATA OUT STROBE: DOSTR, DOSTR are write inputs which cause data from the data bus (D0-D7) to be input to the 82C50A. The data input depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DOSTR, DOSTR inputs. Only an active DOSTR or DOSTR, not both, is used to transmit data to the 82C50A during a write operation. If DOSTR is used as the write input, DOSTR should be tied high. If DOSTR is used as the write input, DOSTR should be tied low. D0-D7 1-8 I/O DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data, control and status information between the 82C50A and the CPU. For character formats of less than 8 bits, D7, D6 and D5 are “don’t cares” for data write operations and 0 for data read ope.


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