DatasheetsPDF.com

MK1574 Dataheets PDF



Part Number MK1574
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description Frame Rate Communications PLL
Datasheet MK1574 DatasheetMK1574 Datasheet (PDF)

I C R O C LOC K MK1574 Frame Rate Communications PLL Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 kHz backplane clock, simplifying clock generation and distribution in communications systems. MicroClock can customize this device for any oth.

  MK1574   MK1574



Document
I C R O C LOC K MK1574 Frame Rate Communications PLL Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 kHz backplane clock, simplifying clock generation and distribution in communications systems. MicroClock can customize this device for any other different frequencies. Features • Packaged in 16 pin narrow (150 mil) SOIC • Exact multiplications stored in the device eliminate the need for external dividers • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • 3.0V to 5.5V operation • Available in commercial (0 to +70 C) or industrial (-40 to +85 C) temperature ranges • For jitter attenuation, use the MK2049 Block Diagram VDD GND 2 2 Output Buffer Output Buffer Output Buffer Output Buffer CLK1 CLK2 CLK3 8kHz (recovered) 4 FS0-3 8kHz Input Clock Input Buffer PLL Clock Synthesis and Control Circuitry CAP1 CAP2 1 Revision 011999 Printed 11/15/00 MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax MDS 1574-01 D I C R O C LOC K Pin Assignment ICLK VDD VDD CAP1 GND CAP2 GND FS0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FS3 N/C FS2 FS1 CLK3 CLK2 CLK1 8KOUT MK1574 Frame Rate Communications PLL Output Clocks Decoding Table MK1574-01 (MHz) Decode Address FS3:0 (Hex) 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 ICLK pin 1 Reserved Reserved Reserved Reserved 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz 8.00kHz Multiplier On-chip Reserved Reserved Reserved Reserved 2940 1960 2760 2640 1920 6480 2112 1578 8192 6176 1024 772 CLK 1 pin 10 Reserved Reserved Reserved Reserved 23.52 15.68 22.08 21.12 15.36 51.84 16.896 12.624 65.536 49.408 8.192 6.176 CLK 2 pin 11 Reserved Reserved Reserved Reserved 11.76 7.84 11.04 10.56 7.68 25.92 8.448 6.312 32.768 24.704 4.096 3.088 CLK 3 pin 12 Reserved Reserved Reserved Reserved 5.88 3.92 5.52 5.28 3.84 12.96 4.224 3.156 16.384 12.352 2.048 1.544 16 pin (150 mil) SOIC • 0 = connect directly to ground, 1 = connect directly to VDD. Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name ICLK VDD VDD CAP1 GND CAP2 GND FS0 8KOUT CLK1 CLK2 CLK3 FS1 FS2 N/C FS3 Type I P P I P I P I O O O O I I I Description Input clock. Connect to an 8kHz clock input. Connect to +3.3V or +5V. Connect to +3.3V or +5V. Must be same voltage as pin 2. Connect a ceramic capacitor and a resistor in series between this pin and CAP2. Refer to page 4. Connect to ground. Connect a ceramic capacitor and a resistor in series between this pin and CAP1. Refer to page 4. Connect to ground. Frequency Select 0. Determines CLK outputs per table above. Recovered 8kHz output clock. Can be lower jitter, better duty cy.


MK1573-02 MK1574 MK1704A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)