M74HCT7259

® M74HCT7259 8BIT ADDRESSABLE LATCH/DECODER/RELAIS DRIVER (OPEN DRAIN,INVERTING OUTPUT) PRELIMINARY DATA LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C s COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN) VIL = 0.8V (MAX) AT 5V s OUTPUT DRIVE CAPABILITY 90 LSTTL LOADS s HIGH CURRENT OPEN DRAIN OUTPUT UP TO 80 mA The M74HCT7259 is a high speed CMOS 8 BIT ADDRESSABLE LATCH/DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. The M74HCT7259 has single data input (D) 8 LATCH inverted OUTPUTS (Q0-Q7), 3 address inputs (A, B and C), common enable input (ENABLE) and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and C inputs. When ENABLE is taken low the data flows through to the address output. The data is stored on the positive-going edge of the ENABLE pulse. All unadressed latches will remain unaffected. With ENABLE in the high state the device is deselected and all latches remain in their previous state, unaffected by changes on the s DIP ORDER CODES PACKAGE DIP SOP T UBE M74HCT7259B1R SOP T& R M74HCT7259M1R M74HCT7259M1RTR data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the ENABLE should be held high (inactive) while the address lines are changing. If ENABLE is held high and CLEAR is taken low a...