M74HC77

M54HC77 M74HC77 4-BIT D-TYPE LATCH . . . . . . . . HIGH SPEED tPD = 10 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS77 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC77F1R M74HC77M1R M74HC77B1R M74HC77C1R DESCRIPTION The M54/74HC77 is a high speed CMOS 4-BIT DTYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. It contains two groups of 2-bit latches controlled by an enable input (G1 2 or G3 4). These two latch groups can be used in different circuits. The data applied to the data inputs (1D, 2D, or 3D, 4D) are transfered to the Q outputs (1Q, 2Q, or 3Q, 4Q) respectively when the enable input (G1 2 or G3 4) is taken high. The Q outputs will follow the data inputs as long as the enable input is kept high. When the enable input is taken low, the information data applied to the data inputs is retained at the Q outputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connectio...