M74HC74

M54HC74 M74HC74 DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR . . . . . . . . HIGH SPEED fMAX = 71 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH = IOL = 4 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS74 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HC74F1R M74HC74M1R M74HC74B1R M74HC74C1R DESCRIPTION The M54/74HC74 is a high speed CMOS DUAL D TYPE FLOP WITH PRESET AND CLEAR fabri2 cated in silicon gate C MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and accomplished by a low on the appropriate input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN CONNECTIONS (top view) NC = No Internal Connection October 1992 1/11 M54/M74HC74 TRUTH TABLE INPUTS CLR L H L H H H X: Don’t Care OUTPUTS D X X X L H X CK X X X Q L H H L H Qn Q H L H H L Qn PR H L L H H H FUNCTION CLEAR PRESET NO CHANGE PIN DESCRIPTION PIN No 1, 13 2, 12 3, 11 SYMBOL 1CLR, 2CLR 1D, 2D ...