M74HC126

M54/74HC125 M54/74HC126 QUAD BUS BUFFERS (3-STATE) . . . . . . . . HIGH SPEED tPD = 8 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT 25 °C OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS BALANCED PROPAGATION DELAYS tPLH = tPHL SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH = 6 mA (MIN.) HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE WITH 54/74LS125/126 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CODES : M54HCXXXF1R M74HCXXXM1R M74HCXXXB1R M74HCXXXC1R DESCRIPTION The M54/74HC125/126 are high speed CMOS QUAD BUS BUFFER (3-STATE) FABRICATED IN SILICON GATE C2MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices require the same 3-STATE control input G to be taken high to make the output go into the high impedance state. All inputs are equipped with protection circuits against static discharge and transient excess voltage. INPUT AND OUTPUT EQUIVALENT CIRCUIT HC126 PIN CONNECTIONS (top view) HC125 NC = No Internal Connection September 1993 1/11 M54/M74HC125/126 CHIP CARRIER HC125 HC126 TRUTH TABLE (HC125) A X L H G H L L Y Z L H TRUTH TABLE (HC126) A X L H G L H H Y Z L H PIN DESCRIPTION (HC125) PIN No 1, 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYMBOL G1 to G4 A1 to A4 Y1 to Y4 GND VCC NAME AND FUNCTION Output Enable Input Data Inputs Data Outputs Ground (0V) Posi...