M68Z128W

M68Z128W 3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable s s LOW VOLTAGE: 3.0V (+0.6V / –0.3V) 128Kb x 8 LOW POWER SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 70ns LOW VCC DATA RETENTION: 1.4V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER INTENDED for USE with ST ZEROPOWER® and TIMEKEEPER® CONTROLLERS TSOP32 (N) 8 x 20mm s s s s s DESCRIPTION The M68Z128W is a 1 Mbit (1,048,576 bit) Fast CMOS SRAM, organized as 131,072 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 3.0V (+0.6V / –0.3V) supply, and all inputs and outputs are TTL compatible. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68Z128W is available in the standard 450mil-wide TSOP type 1 package. Figure 1. Logic Diagram VCC 17 A0-A16 8 DQ0-DQ7 Table 1. Signal Names A0-A16 DQ0-DQ7 E1 E2 G W VCC VSS NC Address Inputs Data Input/Output Chip Enable 1 Chip Enable 2 Output Enable Write Enable W E1 E2 G M68Z128W VSS Supply Voltage Ground Not Connected Internally AI01878B March 2000 1/12 M68Z128W Table 2. Absolute Maximum Ratings (1) Symbol TA TSTG VIO (2) VCC IO (3) PD Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltage Supply Voltage Output Current Power Dissipation Value 0 to 70 –65 to 150 –0.5 to VCC + 0.5 –0.5 to 4.6 20 1 Unit °C °C V V mA W Note: 1. Except for the ...