Document
M36DR232A M36DR232B
32 Mbit (2Mb x16, Dual Bank, Page) Flash Memory and 2 Mbit (128K x16) SRAM, Multiple Memory Product
FEATURES SUMMARY s SUPPLY VOLTAGE – VDDF = VDDS =1.65V to 2.2V
s s s
Figure 1. Packages
– VPPF = 12V for Fast Program (optional) ACCESS TIME: 100,120ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M36DR232A: 00A0h – Bottom Device Code, M36DR232B: 00A1h
FBGA
FLASH MEMORY s 32 Mbit (2Mb x16) BOOT BLOCK – Parameter Blocks (Top or Bottom Location)
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Stacked LFBGA66 (ZA) 8 x 8 ball array
PROGRAMMING TIME – 10µs typical – Double Word Programming Option
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ASYNCRONOUS PAGE MODE READ – Page width: 4 Word – Page Mode Access Time: 35ns
s
DUAL BANK OPERATION – Read within one Bank while Program or Erase within the other – No Delay between Read and Write Operations
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BLOCK PROTECTION ON ALL BLOCKS – WPF for Block Locking COMMON FLASH INTERFACE – 64 bit Security Code
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s s s
SRAM 2 Mbit (128K x 16 bit) LOW VDDS DATA RETENTION: 1V POWER DOWN FEATURES USING TWO CHIP ENABLE INPUTS
November 2001
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M36D232A, M36DR232B
DESCRIPTION The M36DR232 is a multichip memory device containing a 32 Mbit boot block Flash memory and a 4 Mbit of SRAM. The device is offered in a Stacked LFBGA66 (0.8 mm pitch) package. The two components are distinguished by use with three chip enable inputs: EF for the Flash memory and, E1S and E2S for the SRAM. The two components are also separately power supplied and grounded. Figure 2. Logic Diagram
VSSF
Table 1. Signal Names
A0-A16 A17-A20 DQ0-DQ15 VDDF VPPF Address Inputs Address Inputs for Flash Chip only Data Input/Output Flash Power Supply Flash Optional Supply Voltage for Fast Program & Erase Flash Ground SRAM Power Supply SRAM Ground Not Connected Internally
VDDF VPPF VDDS 21 A0-A20 EF GF WF RPF WPF E1S E2S GS WS UBS LBS M36DR232A M36DR232B 16 DQ0-DQ15
VDDS VSSS NC
Flash control functions EF GF WF RPF WPF Chip Enable input Output Enable input Write Enable input Reset input Write Protect input
SRAM control functions E1S, E2S GS WS UBS Chip Enable input Output Enable input Write Enable input Upper Byte Enable input Lower Byte Enable input
VSSF
VSSS
AI05440
LBS
2/46
M36D232A, M36DR232B
Figure 3. LFBGA Connections (Top view through package)
#1
#2
1
2
3
4
5
6
7
8
#3
#4
A
NC
NC
A20
A11
A15
A14
A13
A12
VSSF
NC
NC
NC
B
A16
A8
A10
A9
DQ15
WS
DQ14
DQ7
C
WF
NC
DQ13
DQ6
DQ4
DQ5
D
VSSS
RPF
DQ12
E2S
VDDS
VDDF
E
WPF
VPPF
A19
DQ11
DQ10
DQ2
DQ3
F
LBS
UBS
GS
DQ9
DQ8
DQ0
DQ1
G
A18
A17
A7
A6
A3
A2
A1
E1S
H
NC
NC
NC
A5
A4
A0
EF
VSSF
GF
NC
NC
NC
AI90204
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M36D232A, M36DR232B
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (2) VDDF VDDS VPPF Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Flash Chip Supply Voltage SRAM Chip Supply Voltage Program Voltage
(3)
Value –40 to 85 –40 to 125 –55 to 150 –0.2 to VDD(4) + 0.3 –0.5 to 2.7 –0.2 to 2.6 –0.5 to 13.0
Unit °C °C °C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum voltage may undershoot to –2V during transition and for less than 20ns. 3. Depends on range. 4. VDD = VDDS = VDDF.
Figure 4. Functional Block Diagram
VDDF VPPF
EF GF WF RPF WPF A17-A20 A0-A16 Flash Memory 32 Mbit (x16)
VDDS
VSSF
DQ0-DQ15
E1S E2S GS WS UBS LBS SRAM 2 Mbit (x16)
VSSS
AI05441
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M36D232A, M36DR232B
SIGNAL DESCRIPTIONS See Figure 2 and Table 1. Address Inputs (A0-A16). Addresses A0 to A16 are common inputs for the Flash chip and the SRAM chip. The address inputs for the Flash memory are latched during a write operation on the falling edge of the Flash Chip Enable (EF) or Write Enable (WF), while address inputs for the SRAM array are latched during a write operation on the falling edge of the SRAM Chip Enable lines (E1S or E2S) or Write Enable (WS). Address Inputs (A17-A20). Address A17 to A20 are address inputs for the Flash chip. They are latched during a write operation on the falling edge of Flash Chip Enable (EF) or Write Enable (WF). Data Input/Outputs (DQ0-DQ15). The input is data to be programmed in the Flash or SRAM memory array or a command to be written to the C.I. of the Flash chip. Both are latched on the rising edge of Flash Chip Enable (EF) or Write Enable (WF) and, SRAM Chip Enable lines (E1S or E2S) or Write Enable (WS). The output is data from the Flash memory or SRAM array, the Electronic Signature Manufacturer or Devi.