DatasheetsPDF.com

M368L3223FTN Dataheets PDF



Part Number M368L3223FTN
Manufacturers Sanken electric
Logo Sanken electric
Description 184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC
Datasheet M368L3223FTN DatasheetM368L3223FTN Datasheet (PDF)

256MB, 512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC Revision 1.2 May. 2004 Rev. 1.2 May, 2004 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (August, 2003) - First release Revision 1.1 (August, 2003) - Added K4H560838F based Module. Revision 1.2 (May, 2004) - Modified IDD current spec. DDR SDRAM Rev. 1.2 May, 2004 256MB, 512MB Unbuffered DIMM 184Pin Unbuffered DIMM based on 256Mb F-die (.

  M368L3223FTN   M368L3223FTN


Document
256MB, 512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC Revision 1.2 May. 2004 Rev. 1.2 May, 2004 256MB, 512MB Unbuffered DIMM Revision History Revision 1.0 (August, 2003) - First release Revision 1.1 (August, 2003) - Added K4H560838F based Module. Revision 1.2 (May, 2004) - Modified IDD current spec. DDR SDRAM Rev. 1.2 May, 2004 256MB, 512MB Unbuffered DIMM 184Pin Unbuffered DIMM based on 256Mb F-die (x8, x16) Ordering Information Part Number M368L1624FTM-C(L)B3/AA/A2/B0 M368L3223FTN-C(L)B3/AA/A2/B0 M381L3223FTM-C(L)B3/AA/A2/B0 M368L6423FTN-C(L)B3/AA/A2/B0 M381L6423FTM-C(L)B3/AA/A2/B0 Density 128MB 256MB 256MB 512MB 512MB Organization 16M x 64 32M x 64 32M x 72 64M x 64 64M x 72 DDR SDRAM Component Composition 16Mx16 (K4H561638F) * 4EA 32Mx8 (K4H560838F) * 8EA 32Mx8 (K4H560838F) * 9EA 32Mx8 (K4H560838F) * 16EA 32Mx8 (K4H560838F) * 18EA Height 1,250mil 1,250mil 1,250mil 1,250mil 1,250mil Operating Frequencies B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 166MHz 2.5-3-3 AA(DDR266@CL=2) 133MHz 133MHz 2-2-2 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3 Feature • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1,250 (mil), single (128MB, 256MB), double (512MB) sided SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Rev. 1.2 May, 2004 256MB, 512MB Unbuffered DIMM Pin Configuration (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8 A10 CB6 VDDQ CB7 DDR SDRAM Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back /RAS DQ45 VDDQ /CS0 /CS1 DM5 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Note : 1. * : These pins are not used in this module. 2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72(M381 ~ ) module, and are not used on x64(M368 ~ ) module. 3. Pins 111, 158 are NC for 1row modules [ M368L1624FTM, M368(81)L3223FTN(M)] & used for 2row modules [M368(81)L6423FTN(M) ] . Pin Description Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 (for x72 module) Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Pin Name DM0 ~ 7, 8(for ECC) Data - in mask Power supply (2.5V) Power Supply for DQS(2.5V) Ground Power supply for reference Serial EEPROM Power/Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM No connection Function Rev. 1.2 May, 2004 256MB, 512MB Unbuffered DIMM DDR SDRAM 128MB, 16M x 64 Non ECC Module (M368L1624FTM) (Populated as 1 bank of x16 DDR SDRAM Module) Functional Block Diagram CS0 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/O 6 I/O 4 I/O 1 I/O 3 I/O 2 I/O 0 I/O 5 I/O 7 UDQS UDM I/O 8 I/O 10 I/O 15 I/O 13 I/O 12 I/O 14 I/O 11 I/O 9 CS DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 .


M368L3223ETN M368L3223FTN M368L3223FTN-CB3LAA


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)