Document
M34A02
2 Kbit Serial SMBus EEPROM for ACR Card Configuration
PRODUCT PREVIEW
s s s s s s s s s s
Two Wire SMBus Serial Interface 2.7V to 3.6V Single Supply Voltage Hardware Write Control BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
8 1
SO8 (MN) 150 mil width
DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits, and operate down to 2.7 V. These devices are available in Plastic Small Outline and Thin Shrink Small Outline packages. These devices are written by the ACR card-issuer, and then accessed in Read mode in the application, using the ACR Serial Bus protocol. This is a two wire serial interface that uses a bidirectional data bus and serial clock. The device carries a built-in 4-bit Device Type Identifier code (1011). The device behaves as a slave in the ACR Serial Bus protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition
8 1
TSSOP8 (DW) 169 mil width
Figure 1. Logic Diagram
VCC
3 E0-E2 SDA M34A02
Table 1. Signal Names
E0, E1, E2 SDA SCL WC VCC VSS Chip Enable Serial Data Serial Clock Write Control Supply Voltage Ground
SCL WC
VSS
AI03794
April 2001
This is preliminary information on a new product now in development. Details are subject to change without notice.
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Figure 2. SO and TSSOP Connections Figure 3. Typical ACR Application PCB Connection (showing E2,E1,E0 address 000)
VCC M34A02 E0 E1 E2 VSS 1 2 3 4 8 7 6 5
AI03795
E0 VCC WC SCL SDA E1 E2 VSS VSS
VCC WC SCL SDA RL
ACR Bus
AI04092
Note: 1. This arrangement on the chip enable lines allows the application to start at ACR address 000h.
is followed by a Device Select code and RW bit (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Power On Reset: V CC Lock-Out Write Protect In order to prevent data corruption and inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. The internal reset is held active until VCC has reached the POR Table 2. Absolute Maximum Ratings 1
Symbol TA TSTG TLEAD VIO VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input or Output range Supply Voltage
threshold value, and all operations are disabled – the device will not respond to any command. In the same way, when VCC drops from the operating voltage, below the POR threshold value, all operations are disabled and the device will not respond to any command. A stable and valid V CC must be applied before applying any logic signal. SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this line is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to V CC. (Figure 3 indicates how the value of the pull-up resistor
Value –40 to 125 –65 to 150
Unit °C °C °C V V V
SO8: 20 seconds (max) 2 TSSOP8: 20 seconds (max) 2
235 235 –0.6 to 6.5 –0.3 to 6.5 4000
Electrostatic Discharge Voltage (Human Body model) 3
Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. IPC/JEDEC J-STD-020A 3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
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M34A02
can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value t.