Document
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 256Mb E-die (x4, x8) with 1,700 / 1,200mil Height & 72-bit ECC
Revision 1.4 January, 2004
Revision 1.4 February, 2004
256MB, 512MB, 1GB Registered DIMM
Revision History
Revision 1.0 (April, 2003) - First release Revision 1.1 (July, 2003) - Delete speed B3 Revision 1.2 (August, 2003) - Corrected typo. Revision 1.3 (January, 2004) - Corrected typo in functional block diagram of 1GB DIMM Revision 1.4 (February, 2004) - Corrected functional block diagram of 1GB DIMM
DDR SDRAM
Revision 1.4 February, 2004
256MB, 512MB, 1GB Registered DIMM
184Pin Registered DIMM based on 256Mb E-die (x4, x8)
Ordering Information
Part Number M383L3223ETS-CAA/A2/B0/A0 M383L6423ETS-CAA/A2/B0/A0 M383L6420ETS-CAA/A2/B0/A0 M383L2828ET1-CAA/A2/B0/A0 M312L3223ETS-CAA/A2/B0/A0 M312L6423ETS-CAA/A2/B0/A0 M312L6420ETS-CAA/A2/B0/A0 M312L2828ET0-CAA/A2/B0/A0 Density 256MB 512MB 512MB 1GB 256MB 512MB 512MB 1GB Organization 32M x 72 64M x 72 64M x 72 128M x 72 32M x 72 64M x 72 64M x 72 128M x 72
DDR SDRAM
Component Composition 32Mx8( K4H560838E) * 9EA 32Mx8( K4H560838E) * 18EA 64Mx4( K4H560438E) * 18EA st.128Mx4( K4H510638E) * 18EA 32Mx8( K4H560838E) * 9EA 32Mx8( K4H560838E) * 18EA 64Mx4( K4H560438E) * 18EA st.128Mx4( K4H510638E) * 18EA
Height 1,700mil 1,700mil 1,700mil 1,700mil 1,200mil 1,200mil 1,200mil 1,200mil
Operating Frequencies
AA(DDR266@CL=2) Speed @CL2 Speed @CL2.5 CL-tRCD-tRP 133MHz 133MHz 2-2-2 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3 A0(DDR200@CL=2) 100MHz 2-2-2
Feature
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • 1,700mil / 1,200mil height & double sided
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Revision 1.4 February, 2004
256MB, 512MB, 1GB Registered DIMM
Pin Configuration (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VDD */CS2 DQ48 DQ49 VSS *CK2.