M2V64S30DTP-7

MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x (4-BANK x 2,097,152-WORD x 4-BIT) 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM PRELIMINARY Some of contents are described for general products and are subject to change w ithout notice. DESCRIPTION M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems. FEATURES M2V64S20/30/40DTP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle T ime Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Max.) (Single Bank) (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) V64S20D V64S30D V64S40D Icc6 Self Refresh Current (Max.) -6 7.5ns 45ns 20ns 5.4ns 67.5ns 75mA 75mA 85mA 1mA -7 10ns 50ns 20ns 6ns 70ns 70mA 70mA 80mA 1mA -8 10ns 50ns 20ns 6ns 70ns 70mA 70mA 80mA 1mA - Single 3.3v±0.3V power supply - Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2> - Fully Synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0 & BA1 (Bank...