Document
FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21349-1E
ASSP
Single Serial Input PLL Frequency Synthesizer
On-Chip prescaler
MB15C03
s DESCRIPTION
The Fujitsu MB15C03 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/ 65 division is available for the prescaler that enables pulse swallow operation. This operates with a supply voltage of 1.0 V (min.). MB15C03 is suitable for mobile communications, such as paging systems.
s FEATURES
• Frequency operation • Separate power supply : • • • • 90 MHz @VDD = 1.0 to 1.5V 120 MHz @VDD = 1.2 to 1.5V VDD = 1.0 to 1.5 V (for overall system) VP = 2.0V to 3.5V (for a charge pump)
Power saving function Pulse swallow function: 64/65 Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 6-bit swallow counter: 0 to 63 - Binary 12-bit programmable counter: 5 to 4,095 • Wide operating temperature: Ta = –20 to +60°C • Plastic 16-pin SSOP package (FPT-16P-M05)
s PACKAGE
16-pin, plastic SSOP
(FPT-16P-M05)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB15C03
s PIN ASSIGNMENT
VDD
Clock Data LE fin PS LD DO
1 2 3 4
16 15 14
VSS OSCIN OSCOUT TEST FC fp fr VP
TOP 13 VIEW 5 12 6 7 8 11 10 9
2
MB15C03
s PIN DESCRIPTIONS
Pin no. 1 2 3 4 Pin name VDD Clock Data LE I/O — I I I System 1V 1V 1V 1V Power supply voltage Clock input for the shift register. Data is shifted into the shift register on the rising edge of the clock. Serial data input using binary code. Load enable signal input When LE is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. Prescaler input. A bias circuit and amplifier are at input port. Connection with an external VCO should be done by AC coupling. Power saving mode control. This pin must be set at “L” at Power-ON. PS = “H” ; Normal mode PS = “L” ; Power saving mode Lock detector signal output. When a PLL is locking, LD outputs “H”. When a PLL is not locking, LD outputs “L”. Charge pump output. Phase of the charge pump can be reversed by FC input. The DO output may be inverted by FC input. The relationships between the programmable reference divider output(fr) and the programmable divider output(fp) are shown below; fr > fp : “H” level (FC= “L”), “L” level (FC= “H”) fr = fp : High impedance fr < fp : “L” level (FC= “L”), “H” level (FC= “H”) Power supply for the charge pump. Programmable reference counter output (fr) monitoring pin. Programmable counter output (fp) monitoring pin. Phase comparator input select pin. Test mode select pin. (Pull down resistor) Setting this pin to “H”, test mode becomes available. Please set this pin to ground or open usually. Oscillator output. Connection for an external cr.