SDA2526-5

Nonvolatile Memory 2-Kbit E2PROM with I2C Bus SDA 2526-5 Preliminary Data MOS IC Features q Word-organized programmable nonvolatile memory in q q q q q q q q q n-channel floating-gate technology (E2PROM) 256 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write cycle Reprogramming by means of on-chip control (without external control) Check for end of programming process Data retention > 10 years More than 104 reprogramming cycles per address Compatible with SDA 2526. Exceptions: Conditions for total erase and current consumption ICC Ordering Code Q67100-H5095 P-DIP-8-1 Type SDA 2526-5 Package P-DIP-8-1 Circuit Description I2C Bus Interface The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external pull-up resistor to VCC (open drain output stage). The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains "1", information changes on the data bus indicate the start or the end of data transfer between two components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop condition. During a data transfer the information on the data bus will only change while the ...