MCM69R737A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69R737A/D Advance Information 4M Late Write LVTTL The MCM69R737A/819A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R819A organized as 256K words by 18 bits, and the MCM69R737A organized as 128K words by 36 bits wide are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also. The RAM uses LVTTL 3.3 V inputs and outputs. The synchronous write and byte enables allow writing to individual bytes or the entire word. Byte Write Control Single 3.3 V + 10%, – 5% Operation LVTTL 3.3 V I/O (VDDQ) Register to Register Synchronous Operation Asynchronous Output Enable Boundary Scan (JTAG) IEEE 1149.1 Compatible Differential Clock Inputs Optional x 18 or x 36 organization MCM69R737A/819A–5 = 5 ns MCM69R737A/819A–6 = 6 ns MCM69R737A/819A–7 = 7 ns MCM69R737A/819A–8 = 8 ns Sleep Mode Operation (ZZ Pin) 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 m...