Document
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69R736A/D
Advance Information
4M Late Write HSTL
The MCM69R736A/818A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R818A organized as 256K words by 18 bits, and the MCM69R736A organized as 128K words by 36 bits wide are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also. The RAM uses HSTL inputs and outputs. The adjustable input trip – point (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance. The synchronous write and byte enables allow writing to individual bytes or the entire word. The impedance of the output buffers is programmable allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. • • • • • • • • • • • Byte Write Control Single 3.3 V +10%, – 5% Operation HSTL – I/O (JEDEC Standard JESD8–6 Class I Compatible) HSTL – User Selectable Input Trip–Point HSTL – Compatible Programmable Impedance Output Drivers Register to Register Synchronous Operation Asynchronous Output Enable Boundary Scan (JTAG) IEEE 1149.1 Compatible Differential Clock Inputs Optional x 18 or x 36 organization MCM69R736A/818A–5 = 5 ns MCM69R736A/818A–6 = 6 ns MCM69R736A/818A–7 = 7 ns MCM69R736A/818A–8 = 8 ns • Sleep Mode Operation (ZZ Pin) • 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package
MCM69R736A MCM69R818A
ZP PACKAGE PBGA CASE 999–01
This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 1 8/20/97
© Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM69R736A•MCM69R818A 1
FUNCTIONAL BLOCK DIAGRAM
DATA IN REGISTER DQ DATA OUT REGISTER
SA
ADDRESS REGISTERS
MEMORY ARRAY
SW SBx CK G
SW REGISTERS
CONTROL LOGIC
SS
SS REGISTERS
PIN ASSIGNMENTS TOP VIEW MCM69R736A
1 A B C D E DQc F G DQc H J K L DQd M VDDQ DQd N P R T U DQd DQd NC NC DQd DQd SA NC VSS VSS VSS VSS SA TDI SW SA SA VDD SA TCK VSS VSS VSS VDD SA TDO DQa VDDQ DQa DQa SA NC DQa DQa NC ZZ N P R T NC U SA SA TDI NC TCK SA TDO SA ZZ VDDQ TMS NC VDDQ DQd SBd CK SBa DQa DQa M VDDQ DQb DQb NC NC NC DQb SA VSS VSS VSS VSS SW SA SA VDD VSS VSS VSS VDD NC VDDQ DQa NC SA NC DQa NC DQc DQc DQc SBc VSS Vref VSS NC NC VDD CK SBb VSS Vref VSS DQb DQb DQb DQb H J K L DQc VSS VSS SS G VSS VSS DQb DQb F G NC DQb DQb NC SBb VSS Vref VSS VSS NC NC VDD CK CK VSS VSS Vref VSS SBa NC DQa DQa NC VDDQ DQc DQb VDDQ VDDQ NC NC DQc 2 SA NC SA DQc 3 SA SA SA VSS 4 NC NC VDD ZQ 5 SA SA SA VSS 6 SA NC SA DQb 7 VDDQ NC NC DQb A B C D E NC VDDQ DQb NC VSS VSS SS G VSS VSS NC DQa DQa VDDQ 1 VDDQ NC NC DQb 2 SA NC SA NC
MCM69R818A
3 SA SA SA VSS 4 NC NC VDD ZQ 5 SA SA SA VSS 6 SA NC SA DQa 7 VDDQ NC NC NC
VDDQ VDD DQd DQd
VDD VDDQ DQa DQa
VDDQ VDD NC DQb DQb NC
VDD VDDQ NC DQa DQa NC
VDDQ TMS
NC VDDQ
MCM69R736A•MCM69R818A 2
MOTOROLA FAST SRAM
MCM69R736A PIN DESCRIPTIONS
PBGA Pin Locations 4K 4L (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T 5L, 5G, 3G, 3L (a), (b), (c), (d) 4E 4M 4U 3U 5U 2U 4D 7T 4C, 2J, 4J, 6J, 4R, 5R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3J, 5J 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R 4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U Symbol CK CK DQx Type Input Input I/O Description Address, data in and control input register clock. Active high. Address, data in and control input register clock. Active low. Synchronous Data I/O.
G SA SBx
Input Input Input
Output Enable: Asynchronous pin, active low. Synchronous Address Inputs: Registered on the rising clock edge. Synchronous Byte Write Enable: Enables writes to byte x in conjunction with the SW input. Has no effect on read cycles, active low. Synchronous Chip Enable: Registered on the rising clock edge, active low. Synchronous Write: Registered on the rising clock edge, active low. Writes all enabled bytes. Test Clock (JTAG). Test Data In (JTAG). Test Data Out (JTAG). Test Mode Select (JTAG). Programmable Output Impedance: Programming pin. Enables sleep mode, active high. Core Power Supply. Output Power Supply: provides operating power for output buffers. Input Reference: provides reference voltage for input buffers. Ground. No Connection: There is no connection to .