MCM67Q909

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67Q909/D Advance Information MCM67Q909 512K x 9 Bit Separate I/O Synchronous Fast Static RAM The MCM67Q909 is a 4M–bit static random access memory, organized as 512K words of 9 bits. It features separate TTL input and output buffers, which drive 3.3 V output levels, and incorporates input and output registers on–board with high speed SRAM. It also features transparent–write and data pass–through capabilities. The synchronous design allows for precise cycle control with the use of an external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are registered on the rising edge of clock (K). The control pins (E, W, G) function differently in comparison to most synchronous SRAMs. This device will not deselect with E high. The RAM remains active at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G is registered low. The transparent write feature allows the output data to track the input data. E, G, and W must be asserted to perform a transparent write (write and pass–through). The input data is available at the ouputs on the next rising edge of clock (K). The pass–through function is always enabled. E high disables the write to the array while allowing a pass–through cycle to occur on the next rising edge of clock (K). Only a registered G high will three–state the outputs. The MCM67Q909 ...