MCM67J618B

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67J618B/D Product Preview MCM67J618B 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Registered Outputs The MCM67J618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. This device contains output registers for pipeline operations. At the rising edge of K, the RAM provides the output data from the previous cycle. Output enable (G) is asynchronous for maximum system design flexibility. Burst can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM67...