DatasheetsPDF.com

MCM67H518 Dataheets PDF



Part Number MCM67H518
Manufacturers Motorola
Logo Motorola
Description 32K x 18 Bit BurstRAM Synchronous Fast Static RAM
Datasheet MCM67H518 DatasheetMCM67H518 Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67H518/D 32K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67H518 is a 589,824 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 32,768 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates inpu.

  MCM67H518   MCM67H518


Document
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67H518/D 32K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67H518 is a 589,824 bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 32,768 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A14), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM67H518 (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased flexibility for incoming signals. Dual write enables (LW and UW) are provided to allow individually writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17 (the upper bits). This device is ideally suited for systems that require wide data bus widths and cache memory. See Figure 2 for applications information. • • • • • • • • • • • Single 5 V ± 5% Power Supply Fast Access Times: 9/10/12 ns Max Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package ADSP Disabled with Chip Enable (E) – Supports Address Pipelining MCM67H518 FN PACKAGE PLASTIC CASE 778–02 PIN ASSIGNMENT A6 A7 E UW LW ADSC ADSP ADV K G A8 A9 A10 DQ9 DQ10 VCC VSS DQ11 DQ12 DQ13 DQ14 VSS VCC DQ15 DQ16 DQ17 7 6 5 4 3 2 1 52 51 50 49 48 47 8 46 9 45 10 44 11 43 12 42 13 41 14 40 15 39 16 38 17 37 18 36 19 35 20 34 21 22 23 24 25 26 27 28 29 30 31 32 33 A5 A4 A3 A2 A1 A0 VSS VCC NC A14 A13 A12 A11 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 PIN NAMES A0 – A14 . . . . . . . . . . . . . . . . Address Inputs K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock ADV . . . . . . . . . . . . Burst Address Advance LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Upper Byte Write Enable ADSC . . . . . . . . . Controller Address Status ADSP . . . . . . . . . Processor Address Status E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 – DQ17 . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . . . . No Connection All power supply and ground pins must be connected for proper operation of the device. BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp. REV 3 5/95 © Motorola, Inc. 1994 MOTOROLA FAST SRAM MCM67H518 1 BLOCK DIAGRAM (See Note) ADV BURST LOGIC Q0 BINARY COUNTER K A0 15 Q1 A1 A1′ INTERNAL A0′ ADDRESS 32K x 18 MEMORY ARRAY ADSC ADSP A0 – A14 ADDRESS REGISTER CLR 2 A1 – A0 15 A2 – A14 18 9 9 UW LW WRITE REGISTER DATA–IN REGISTERS E ENABLE REGISTER 9 9 9 9 OUTPUT BUFFER G DQ0 – DQ8 DQ9 – DQ17 NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP and E are sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP–initiated two cycle WRITE can be performed by asserting ADSP, E, and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram). Note that when E and ADSC are high, ADSP is ignored – the external address is not registered in this case. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only .


MCM67D709 MCM67H518 MCM67H618A


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)