MCM67C618A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67C618A/D 64K x 18 Bit BurstRAM™ Synchronous Fast Static RAM With Burst Counter and Registered Outputs The MCM67C618A is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486™ and Pentium™ microprocessors. It is organized as 65,536 words of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive registered output drivers onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except output enable (G) are clock (K) controlled through positive–edge– DQ9 triggered noninverting registers. DQ10 This device contains output registers for pipeline operations. At the risVCC ing edge of K, the RAM provides the output data from the previous cycle. VSS Output enable (G) is asynchronous for maximum system design flexibilDQ11 ity. DQ12 Burst can be initiated with either address status processor (ADSP) or adDQ13 dress status cache controller (ADSC) input pins. Subsequent burst adDQ14 dresses can be generated internally by ...