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MCM67A618B Dataheets PDF



Part Number MCM67A618B
Manufacturers Motorola
Logo Motorola
Description 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM
Datasheet MCM67A618B DatasheetMCM67A618B Datasheet (PDF)

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67A618B/D Advance Information MCM67A618B 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM The MCM67A618B is a 1,179,648 bit latched address static random access memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enab.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM67A618B/D Advance Information MCM67A618B 64K x 18 Bit Asynchronous/ Latched Address Fast Static RAM The MCM67A618B is a 1,179,648 bit latched address static random access memory organized as 65,536 words of 18 bits. The device integrates a 64K x 18 SRAM core with advanced peripheral circuitry consisting of address and data input latches, active low chip enable, separate upper and lower byte write strobes, and a fast output enable. This device has increased output drive capability supported by multiple power pins. Address, data in, and chip enable latches are provided. When latch enables (AL for address and chip enables and DL for data in) are high, the address, data in, and chip enable latches are in the transparent state. If latch enables are tied high the device can be used as an asynchronous SRAM. When latch enables are low the address, data in, and chip enable latches are in the latched state. This input latch simplifies read and write cycles by guaranteeing address and data–in hold time in a simple fashion. DQ9 Dual write enables (LW and UW) are provided to allow individually DQ10 writeable bytes. LW controls DQ0 – DQ8 (the lower bits) while UW VCC controls DQ9 – DQ17 (the upper bits). VSS Six pair of power and ground pins have been utilized and placed on DQ11 the package for maximum performance. DQ12 The MCM67A618B will be available in a 52–pin plastic leaded chip DQ13 carrier (PLCC). DQ14 This device is ideally suited for systems that require wide data bus VSS VCC widths, cache memory, and tag RAMs. • • • • • • • • • Single 5 V ± 5% Power Supply Fast Access Times: 10/12/15 ns Max Byte Writeable via Dual Write Enables Separate Data Input Latch for Simplified Write Cycles Address and Chip Enable Input Latches Common Data Inputs and Data Outputs Output Enable Controlled Three–State Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package DQ15 DQ16 DQ17 FN PACKAGE PLASTIC CASE 778–02 PIN ASSIGNMENT A6 A7 E UW LW VCC V SS DL AL G A8 A9 A10 7 6 5 4 3 2 1 52 51 50 49 48 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 DQ8 DQ7 DQ6 VCC VSS DQ5 DQ4 DQ3 DQ2 VSS VCC DQ1 DQ0 All power supply and ground pins must be connected for proper operation of the device. A5 A4 A3 A2 A1 A0 V SS V CC A15 A14 A13 A12 A11 PIN NAMES A0 – A15 . . . . . . . . . . . . . . . . Address Inputs AL . . . . . . . . . . . . . . . . . . . . . . Address Latch DL . . . . . . . . . . . . . . . . . . . . . . . . . Data Latch LW . . . . . . . . . . . . Lower Byte Write Enable UW . . . . . . . . . . . . Higher Byte Write Enable E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable G . . . . . . . . . . . . . . . . . . . . . . Output Enable DQ0 – DQ17 . . . . . . . . . . . Data Input/Output VCC . . . . . . . . . . . . . . . . + 5 V Power Supply VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 2 7/16/97 © Motorola, Inc. 1997 MOTOROLA FAST SRAM MCM67A618B 1 BLOCK DIAGRAM A0 – A15 16 LATCH 16 MEMORY ARRAY 64K x 18 18 OUTPUT BUFFER DQ0 – DQ17 18 18 9 9 WRITE AMP E LATCH CONTROL 18 LATCH AL LW UW G DL TRUTH TABLE E H L L L L L L L LW X X X H H L L L UW X X X H H L L H AL* X L H X X X X X DL* X X X X X L H X G X X X L H X X X Mode Deselected Cycle Read or Write Using Latched Addresses Read or Write Using Unlatched Addresses Read Cycle Read Cycle Write Both Bytes Using Latched Data In Write Both Bytes Using Unlatched Data In Write Cycle, Lower Byte Supply Current ISB ICC ICC ICC ICC ICC ICC ICC I/O Status High–Z — — Data Out High–Z High–Z High–Z High–Z L H L X X X Write Cycle, Lower Byte ICC High–Z *E and Addresses satisfy the specified setup and hold times for the falling edge of AL. Data–in satisfies the specified setup *and hold times for falling edge of DL. NOTE: This truth table shows the application of each function. Combinations of these functions are valid. ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0) Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC Output Current (per I/O) Power Dissipation Temperature Under Bias Ambient Temperature Storage Temperature Symbol VCC Vin, Vout Iout PD Tbias TA Value – 0.5 to 7.0 – 0.5 to VCC + 0.5 ± 30 1.6 – 10 to + 85 0 to + 70 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit. This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. This device contains circuitry that will ensure the output devices are in High–Z at power up. T.


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