MCM6227A

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6227A/D 1M x 1 Bit Static Random Access Memory The MCM6227A is a 1,048,576 bit static random–access memory organized as 1,048,576 words of 1 bit, fabricated using high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low–power standby mode, remaining in that state until E goes low again. The MCM6227A is available in 400 mil, 28–lead surface–mount SOJ packages. Single 5 V ± 10% Power Supply Fast Access Times: 20, 25, 35, and 45 ns Equal Address and Chip Enable Access Times Input and Output are TTL Compatible Three–State Output Low Power Operation: 160/140/130/120 mA Maximum, Active AC MCM6227A WJ PACKAGE 400 MIL SOJ CASE 810–03 PIN ASSIGNMENT A0 A1 A2 A3 A4 A5 NC A6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A19 A18 A17 A16 A15 A14 NC A13 A12 A11 A10 D E BLOCK DIAGRAM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER MEMORY MATRIX 1024 ROWS x 1024 COLUMNS V CC VSS A7 A8 A9 Q W VSS PIN NAMES A0 – A19 . . . . . . . . . . . . . Address Inputs W . . . . . . . . . . . . . . . . . . . . . Write Enable E . . . . . . . . . . . . . . . . . . . . . . Chip Enable D . . . . . . . . . . . . . . . . . . . . . . . . Dat...