MCM6205D

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6205D/D 32K x 9 Bit Fast Static RAM The MCM6205D is fabricated using Motorola’s high–performance silicon–gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability. This device meets JEDEC standards for functionality and pinout, and is available in a plastic small–outline J–leaded package. Single 5 V ± 10% Power Supply Fully Static — No Clock or Timing Strobes Necessary Fast Access Times: 15, 20, and 25 ns Equal Address and Chip Enable Access Times Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems Low Power Operation: 130 – 140 mA Maximum AC Fully TTL Compatible — Three State Output MCM6205D J PACKAGE 300 MIL SOJ CASE 857–02 PIN ASSIGNMENT NC NC A8 A7 A6 A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 V CC A14 E2 W A13 A9 A10 A11 G A12 E1 DQ8 DQ7 DQ6 DQ5 DQ4 BLOCK DIAGRAM A4 A3 A1 A3 A4 A6 A7 A9 A10 A11 ROW DECODER MEMORY MATRIX 256 ROWS x 128 x 9 COLUMNS VCC VSS A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS PIN NAMES DQ0 DQ8 INPUT DATA CONTROL COLUMN I/O COLUMN DECODER A0 – A14 . . . . . . . . . . . . . Address Input DQ0 – DQ8 . . . Data Input/Data Output W . . . . . . . . . . . . . . . . . . . . Write Enable G . . . . . . . . . . . . . . . . . . . Output Enable E1, E2 . . . . . . . . . . . . . . ...