M48Z35AV

M48Z35AV 5.0 V or 3.3 V, 256 Kbit (32 Kbit x 8) ZEROPOWER® SRAM Not recommended for new design Features ■ Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time )■ Battery low flag (BOK) t(s■ Automatic power-fail chip deselect and WRITE cprotection du■ WRITE protect voltage: ro(VPFD = power-fail deselect voltage) P– M48Z35AV: 2.7 V ≤ VPFD ≤ 3.0 V te■ Self-contained battery in the CAPHAT™ DIP lepackage o■ Packaging includes a 28-lead SOIC and sSNAPHAT® top (to be ordered separately) Ob■ Pin and function compatible with JEDEC -standard 32 Kbit x 8 SRAMs t(s)■ SOIC package provides direct connection for a SNAPHAT® top which contains the battery c■ RoHS compliant Obsolete Produ– Lead-free second level interconnect 28 1 PCDIP28 Battery CAPHAT™ SNAPHAT® battery 28 1 SOH28 June 2011 Doc ID 6784 Rev 9 This is information on a product still in production but not recommended for new designs....