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M48Z30 Dataheets PDF



Part Number M48Z30
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description CMOS 32K x 8 ZEROPOWER SRAM
Datasheet M48Z30 DatasheetM48Z30 Datasheet (PDF)

M48Z30 M48Z30Y CMOS 32K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x 8 SRAMs AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION CHOICE of TWO WRITE PROTECT VOLTAGES: – M48Z30: 4.5V ≤ VPFD ≤ 4.75V – M48Z30Y: 4.2V ≤ VPFD ≤ 4.50V BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED 28 1 PMDIP28 (PM) M.

  M48Z30   M48Z30



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M48Z30 M48Z30Y CMOS 32K x 8 ZEROPOWER SRAM INTEGRATED LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT and BATTERY CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS of DATA RETENTION in the ABSENCE of POWER PIN and FUNCTION COMPATIBLE with JEDEC STANDARD 32K x 8 SRAMs AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION CHOICE of TWO WRITE PROTECT VOLTAGES: – M48Z30: 4.5V ≤ VPFD ≤ 4.75V – M48Z30Y: 4.2V ≤ VPFD ≤ 4.50V BATTERY INTERNALLY ISOLATED UNTIL POWER IS APPLIED 28 1 PMDIP28 (PM) Module Figure 1. Logic Diagram DESCRIPTION The M48Z30/30Y 32K x 8 ZEROPOWER® RAM is a non-volatile 262,144 bit Static RAM organized as 32,768 words by 8 bits. The device combines an internal lithium battery and a full CMOS SRAM in a plastic 28 pin DIP Module. The ZEROPOWER Table 1. Signal Names A0 - A14 DQ0 - DQ7 E G W VCC VSS Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground July 1994 1/12 M48Z30, M48Z30Y Table 2. Absolute Maximum Ratings Symbol TA TSTG TBIAS TSLD VIO VCC Parameter Ambient Operating Temperature Storage Temperature (V CC Off) Temperature Under Bias Lead Soldering Temperature for 10 seconds Input or Output Voltages Supply Voltage Value 0 to 70 –40 to 70 –10 to 70 260 –0.3 to 7 –0.3 to 7 Unit °C °C °C °C V V Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings conditions for extended periods of time may affect reliability. CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode. Table 3. Operating Modes Mode Deselect Write Read Read Deselect Deselect Note: X = VIH or VIL VCC 4.75V to 5.5V or 4.5V to 5.5V E VIH VIL VIL VIL G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode VSO to VPFD (min) ≤ VSO X X Figure 2. DIP Pin Connections DESCRIPTION (cont’d) RAM directly replaces industry standard SRAMs. It also fits into many EPROM and EEPROM sockets, providing the nonvolatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The M48Z30/30Y has its own Power-fail Detect Circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operations brought on by low VCC. As VCC falls below approximately3V, the control circuitry connectsthe battery which sustains data until valid power returns. READ MODE The M48Z30/30Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 262,144 locations in the static storage array. Thus, the unique address 2/12 M48Z30, M48Z30Y Figure 3. Block Diagram specified by the 15 Address Inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within tAVQV (Address Access Time) after the last address input signal is stable, providing that the E and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access Time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until t AVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until the next Address Access. WRITE MODE The M48Z30/30Yis in the Write Mode whenever W and E are active. The start of a write is referenced from the latter occurring falling edge of W or E. AC MEASUREMENT CONDITIONS Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 5ns 0 to 3V 1.5V Note that Output Hi-Z is defined as the point where data is no longer driven. Figure 4. AC Testing Load Circuit 3/12 M48Z30, M48Z30Y Table 4. Capacitance (1, 2) (TA = 25 °C, f = 1 MHz ) Symbol C IN CIO (3) Parameter Input Capacitance Input / Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 10 10 Unit pF pF Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected Table 5. DC Characteristics (TA = 0 to 70°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V) Symbol ILI ILO (1) (1) Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (S.


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