M48Z128V

M48Z128 M48Z128Y, M48Z128V* 5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM FEATURES SUMMARY s INTEGRATED, ULTRA LOW POWER SRAM, POWER-FAIL CONTROL CIRCUIT, and BATTERY s Figure 1. 32-pin PMDIP Module CONVENTIONAL SRAM OPERATION; UNLIMITED WRITE CYCLES 10 YEARS OF DATA RETENTION IN THE ABSENCE OF POWER BATTERY INTERNALLY ISOLATED UNTIL POWER IS FIRST APPLIED AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) – M48Z128: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V – M48Z128Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V – M48Z128V: VCC = 3.0 to 3.6V 2.8V ≤ VPFD ≤ 3.0V SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY SNAPHAT HOUSING (BATTERY) IS REPLACEABLE PIN and FUNCTION COMPATIBLE WITH JEDEC STANDARD 128K x 8 SRAMs EQUIVALENT SURFACE-MOUNT (SMT) SOLUTION REQUIRES A 28-PIN M40Z300/W and A STAND-ALONE 128K x8 LPSRAM (SNAPHAT® Top to be ordered separately) 32 1 s s s s PMDIP32 (PM) Module s s s s * Contact Local Sales Office October 2003 Rev. 3.4 1/21 M48Z128, M48Z128Y, M48Z128V* TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...