M48Z08

M48Z08, M48Z18 5 V, 64 kbit (8 kbit x 8) ZEROPOWER® SRAM Datasheet - production data 28 1 PDIP 28.7 Battery CAPHAT™ Features Integrated, ultra-low power SRAM and powerfail control circuit Unlimited WRITE cycles READ cycle time equals WRITE cycle time Automatic power-fail chip deselect and WRITE protection WRITE protect voltages (VPFD = power-fail deselect voltage): – M48Z08: VCC = 4.75 to 5.5 V 4.5 V ≤ VPFD ≤ 4.75 V – M48Z18: VCC = 4.5 to 5.5 V 4.2 V ≤ VPFD ≤ 4.5 V Self-contained battery in the CAPHAT™ DIP package Pin and function compatible with JEDEC standard 8 kbit x 8 SRAMs RoHS compliant – Lead-free second level interconnect Description The M48Z08/18 ZEROPOWER® RAM is a 8 kbit x 8 non-volatile static RAM which is pin and function compatible with the DS1225. The monolithic chip provides a highly integrated battery-backed memory solution. The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8 kbit x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28-pin, 600 mil DIP CAPHAT™ houses the M48Z08/18 silicon with a long-life lithium button cell in a single package. January 2024 This is information on a product in full production. DocID02424 Rev 10 1/18 www.st.com Contents Contents M48Z08, M48Z18 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . ...