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MGP3006X Dataheets PDF



Part Number MGP3006X
Manufacturers Siemens
Logo Siemens
Description GHz PLL with I2C Bus and Four Chip Addresses
Datasheet MGP3006X DatasheetMGP3006X Datasheet (PDF)

GHz PLL with I2C Bus and Four Chip Addresses MGP 3006X Bipolar IC Features q q q q q q 1-chip system for MPU-control (I2C Bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability 2 high-current band switch outputs (20 mA) Software-compatible with SDA 3202 series Oxis III technology P-DSO-14-1 Type MGP 3006X MGP 3006X Ordering Code Q67000-H5114 Q67006-H5114 Package P-DSO-14-1 (SMD) P-DSO-14-1 Tape & Reel (SMD) Combined with a VCO (t.

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GHz PLL with I2C Bus and Four Chip Addresses MGP 3006X Bipolar IC Features q q q q q q 1-chip system for MPU-control (I2C Bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability 2 high-current band switch outputs (20 mA) Software-compatible with SDA 3202 series Oxis III technology P-DSO-14-1 Type MGP 3006X MGP 3006X Ordering Code Q67000-H5114 Q67006-H5114 Package P-DSO-14-1 (SMD) P-DSO-14-1 Tape & Reel (SMD) Combined with a VCO (tuner), the MGP 3006X device, with four hard-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with PLL-frequency synthesis tuning. The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillator between 16 and 1300 MHz in increments of 62.5 kHz, and, with a 2.4-GHz prescaler 1/2, in the TV-SAT band in increments of 125 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The I2C Bus noise immunity has been improved by a factor of 10 compared to the SDA 3202-2, and the new crystal oscillator generates a sinusoidal signal, suppressing the higher-order harmonics, which reduces the moiré noise considerably. Semiconductor Group 1 04.93 MGP 3006X Circuit Description Tuning Section UHF/VHF REF The tuner signal is capacitively coupled at the UHF/VHF-input and subsequently amplified. The reference input REF should be decoupled to ground using a capacitor of low series inductance. The signal passes through an asynchronous divider with a fixed ratio of P = 8, an adjustable divider with ratio N = 256 through 32767, and is then compared in a digital frequency/phase detector to a reference frequency fREF = 7.8125 kHz. This frequency is derived from a balanced, low-impedance 4-MHz crystal oscillator (pin Q1, Q2) by dividing its output signal by Q = 512. The phase detector has two outputs UP and DOWN that drive the two current sources I+ and I– of a charge pump. If the negative edge of the divided VCO-signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I– current source pulses. PD, UD If the two signals are in phase, the charge pump output (PD) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external output transistor at UD and external RC-circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. UD may be switched off by the control bit OS to allow external adjustments. By means of a control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO-gains in the different TV-bands can be compensated, for example. P1, P2 P7 CAU The software-switched outputs P1, P2 can be used for direct band selection (20 mA current output). P7 is a general-purpose open-collector output. The test bit T1 = 1 switches the test signal Cy (divided input signal) to P7. Four different chip addresses can be set by appropriate connection of pin CAU. Q1, Q2 Semiconductor Group 2 MGP 3006X I2C Bus Interface Data are exchanged between the processor and the PLL on the I2C Bus. SCL, SDA The clock is generated by the processor (input SCL), while pin SDA works as an input or output depending on the direction of the data (open collector; external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhances the noise immunity of the I2C Bus. The data from the processor pass through an I2C Bus control. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are high). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes low, while SCL remains high. Stop condition: SDA goes high while SCL remains high. All further information transfer takes place during SCL = low, and the data is forwarded to the control logic on the positive clock edge. The table “bit allocation” should be referred to in the following paragraph. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA-line to low (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The eighth bit is always low. In the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. In.


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