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IDT54FCT88915TT Dataheets PDF



Part Number IDT54FCT88915TT
Manufacturers Integrated Device
Logo Integrated Device
Description LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
Datasheet IDT54FCT88915TT DatasheetIDT54FCT88915TT Datasheet (PDF)

IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc. LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) IDT54/74FCT88915TT 55/70/100/133 PRELIMINARY FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 133MHz • Pin and function compatible with MC88915T • 5 non-inverting outputs, one inverting output, one 2x output, one ÷ 2 out.

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IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc. LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) IDT54/74FCT88915TT 55/70/100/133 PRELIMINARY FEATURES: • 0.5 MICRON CMOS Technology • Input frequency range: 10MHz – f2Q Max. spec (FREQ_SEL = HIGH) • Max. output frequency: 133MHz • Pin and function compatible with MC88915T • 5 non-inverting outputs, one inverting output, one 2x output, one ÷ 2 output; all outputs are TTL-compatible • 3-State outputs • Output skew < 500ps (max.) • Duty cycle distortion < 500ps (max.) • Part-to-part skew: 1ns (from tPD max. spec) • TTL level output voltage swing • 64/–15mA drive at TTL output voltage levels • Available in 28 pin PLCC, LCC and SSOP packages DESCRIPTION: The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially delay across the device. The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO. The VCO is designed for a 2Q operating frequency range of 40MHz to f2Q Max. The IDT54/74FCT88915TT provides 8 outputs with 500ps skew. The Q5 output is inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the Q frequency. The FREQ_SEL control provides an additional ÷ 2 option in the output path. PLL _EN allows bypassing of the PLL, which is useful in static test modes. When PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (PLL_EN = 1). The LOCK output attains logic HIGH when the PLL is in steady-state phase and frequency lock. When OE/ RST is low, all the outputs are put in high impedance state and registers at Q, Q and Q/2 outputs are reset. The IDT54/74FCT88915TT requires one external loop filter component as recommended in Figure 1. FUNCTIONAL BLOCK DIAGRAM FEEDBACK Phase/Freq. Detector Voltage Controlled Oscilator LF REF_SEL PLL_EN 0 1 Mux 2Q (÷1) (÷2) 1 M u x 0 D Q LOCK 0M u 1x SYNC (0) SYNC (1) Charge Pump Q0 Q1 Divide -By-2 FREQ_SEL OE/RST CP R Q D CP R D CP R D CP R D CP R D CP D CP R R Q Q Q2 Q Q3 Q Q4 Q5 Q Q Q/2 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 3072 drw 01 MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1995 Integrated Device Technology, Inc. AUGUST 1995 DSC-4247/1 9.7 9.7 1 1 IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CMOS CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OE/RST GND VCC VCC Q5 Q4 2Q 4 FEEDBK REF_SEL SYNC(0) VCC(AN) LF GND(AN) SYNC(1) 5 6 7 8 9 10 11 12 3 2 1 28 27 26 25 24 23 Q/2 GND Q3 VCC Q2 GND LOCK GND Q5 VCC OE/RST FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SO28-7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Q4 VCC 2Q Q/2 GND Q3 VCC Q2 GND LOCK PLL_EN GND Q1 VCC 3072 drw 03 J28-1, L28-1 22 21 20 SYNC(1) FREQ_SEL GND Q0 13 14 15 16 17 18 Q1 GND GND FREQ_SEL PLL_EN 3072 drw 02 PLCC/LCC TOP VIEW VCC Q0 SSOP TOP VIEW PIN DESCRIPTION Pin Name SYNC(0) SYNC(1) REF_SEL FREQ_SEL FEEDBACK LF Q0-Q4 Q5 2Q Q/2 LOCK OE/RST PLL_EN I/O I I I I I I O O O O O I I Reference clock input. Reference clock input. Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram). Selects between ÷1 and ÷2 frequency options. (Refer to functional block diagram). Feedback input to phase detector. Input for external loop filter connection. Clock output. Inverted clock output. Clock output (2 x Q frequency). Clock output (Q frequency ÷ 2). Indicates phase lock has been achieved (HIGH when locked). Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in HIGH impedance. Disables phase-lock for low frequency testing. (Refer to functional block diagram). 3072 tbl 01 Description 9.7 2 IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating VTERM(2) Terminal Voltage with Respect to GND (3) VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature I OUT DC Output Current Commercial –0.5 to +7.0 Military –0.5 to +7.0 Unit V CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. 6.0 8.0 Unit pF pF 3072 lnk 03 –0.5 to VCC +0.5 0 to +70 –55 to +125 –55 to +125 –60 to +120 –0.5 to VCC +0.5 –55 to +125 –65 to +135 –65 to +150 –60 to +120 V °C °C °C mA NOTE: 1. This parameter is measured at characterization but not tested. 3.


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