5120 x 8-BIT LINE MEMORY (FIFO)
MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66256FP M66256FP
5120 × 8-BIT LINE MEMORY (FIFO) 5120 × 8-BIT LI...
Description
MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66256FP M66256FP
5120 × 8-BIT LINE MEMORY (FIFO) 5120 × 8-BIT LINE MEMORY (FIFO)
DESCRIPTION The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput. FEATURES Memory configuration ........................................................ ............................. 5120 words × 8-bits (dynamic memory) High-speed cycle ............................................. 25ns (Min.) High-speed access ......................................... 18ns (Max.) Output hold ........................................................ 3ns (Min.) Fully independent, asynchronous write and read operations Variable length delay bit Output .................................................................... 3 states APPLICATION Digital photocopiers, high-speed facsimile, laser beam printers.
PIN CONFIGURATION (TOP VIEW)
Q0 ← 1 Q1 ← 2 DATA OUTPUT Q2 ← 3 Q3 ← 4 READ ENABLE INPUT RE → 5
24 ← D0 23 ← D1 22 ← D2 21 ← D3 20 ← WE WRITE ENABLE INPUT DATA INPUT
M66256FP
READ RESET INPUT RRES→ 6 GND 7 READ CLOCK INPUT RCK → 8 Q4 ← 9 Q5 ← 10 DATA OUTPUT Q6 ← 11 Q7 ← 12
19 ← WRES WRITE RESET INPUT 18 VCC 17 ← WCK WRITE CLOCK INPUT 16 ← D4 15 ← D5 1...
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