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MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66220SP/FP M66220SP/FP
× 8-BIT MAIL-BOX 256256 × 8-BIT MAIL-BOX
DESCRIPTION
The M66220 is a mail box that incorporates a complete CMOS shared memory cell of 256 × 8-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
PIN CONFIGURATION (Top view)
CHIP SELECT CSA → 1 INPUT WRITE ENABLE WEA → 2 INPUT NOT READY Not Ready A← 3 OUTPUT OUTPUT ENABLE OEA → INPUT A 0A → A 1A → A 2A → A PORT A3A → ADDRESS INPUT A 4A → A 5A → A 6A → A 7A → I/O0A ↔ I/O1A ↔ I/O2A ↔ ↔ A PORT I/O3A DATA I/O ↔ 4 A I/O I/O5A ↔ I/O6A ↔ I/O7A ↔ GND 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 VCC CHIP SELECT 41 ← CSB INPUT WRITE ENABLE 40 ← WEB INPUT 39 → Not Ready B NOT READY OUTPUT 38 ← OEB OUTPUT ENABLE INPUT 37 ← A0B 36 ← A1B 35 ← A2B 34 ← A3B B PORT ADDRESS 33 ← A4B INPUT 32 ← A5B 31 ← A6B 30 ← A7B 29 ↔ I/O7B 28 ↔ I/O6B 27 ↔ I/O5B 26 ↔ I/O4B B PORT DATA I/O 25 ↔ I/O3B 24 ↔ I/O2B 23 ↔ I/O1B 22 ↔ I/O0B
FEATURES
• • • • • • • • • • Memory configuration of 256 × 8 bits High-speed access, address access time 40ns (typ.) Complete asynchronous accessibility from ports A and B Completely static operation Built-in port arbitration function Low power dissipation CMOS design 5V single power supply Not Ready output pin is provided (open drain output) TTL direct-coupled I/O 3-state output for I/O pins
M66220SP/FP
APPLICATION
Inter-MPU data transfer memory, buffer memory for image processing system.
Outline 42P4B 42P2R-A
BLOCK DIAGRAM
NOT READY OUTPUT Not Ready A 3 WRITE WEA 2 ENABLE INPUT CHIP CSA 1 SELECT INPUT OUTPUT OEA 4 ENABLE INPUT I/O0A 13 I/O1A 14 I/O2A 15 I/O3A 16 A PORT DATA I/O I/O4A 17 I/O5A 18 I/O6A 19 I/O7A 20 A0A A1A A2A A3A A4A A5A A6A A7A 5 6 7 8 9 10 11 12
VCC 42
NOT READY 39 Not Ready B OUTPUT WRITE ENABLE INPUT CHIP 41 CSB SELECT INPUT OUTPUT 38 OEB ENABLE INPUT 22 I/O0B 23 I/O1B 24 I/O2B 25 I/O3B B PORT DATA I/O 26 I/O4B 27 I/O5B 28 I/O6B 29 I/O7B 40 WEB 37 36 35 34 33 32 31 30 A0B A 1B A 2B A 3B A 4B A 5B A 6B A 7B
CONTROL CIRCUIT
ARBITRATION CIRCUIT
CONTROL CIRCUIT
~
A7A 8 I/O BUFFER
A 7B I/O BUFFER 8
A PORT ADDRESS INPUT
8 ROW/COLUMN DECODER
MEMORY ARRAY OF 256-WORD × 8-BIT CONFIGURATION
~
OEA
WEA
A0A
A0B
WEB
OEB
ROW/COLUMN DECODER
8
B PORT ADDRESS INPUT
21
GND
1
MITSUBISHI 〈DIGITAL ASSP〉
M66220SP/FP
256 × 8-BIT MAIL-BOX
FUNCTION
The M66220 is a mail box most suitable for inter-MPU data transfer which is used in a multiport mode. Provision of two pairs of addresses and data buse.
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