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M64893GP Dataheets PDF



Part Number M64893GP
Manufacturers Mitsubishi
Logo Mitsubishi
Description SERIAL INPUT PLL FREQUENCY SYNTHESIZER
Datasheet M64893GP DatasheetM64893GP Datasheet (PDF)

MITSUBISHI ICS (TV) M64893FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION The M64893 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using Bip process. It contains the prescaler with operating up to 1.3GHz, 4 band drivers and Op. Amp for direct tuning. PIN CONFIGURATION (TOP VIEW) PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 fin GND VCC1 VCC2 BS4 1 2 16 Xin 15 ENA FEATURES 3 4 5 6 7 8 14 DATA 13 CLK CRYSTAL OSCILLAT.

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MITSUBISHI ICS (TV) M64893FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION The M64893 is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using Bip process. It contains the prescaler with operating up to 1.3GHz, 4 band drivers and Op. Amp for direct tuning. PIN CONFIGURATION (TOP VIEW) PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 fin GND VCC1 VCC2 BS4 1 2 16 Xin 15 ENA FEATURES 3 4 5 6 7 8 14 DATA 13 CLK CRYSTAL OSCILLATOR ENABLE INPUT DATA INPUT CLOCK INPUT M64893FP/GP • • • • • • • • • 4 integrated PNP band drivers (Io=40mA,Vsat=0.2V typ@Vcc1 to 13.2V) Built-in Op. Amp for direct tuning voltage output (33V) Low power dissipation (Icc=20mA, Vcc1=5V) Built-in prescaler with input amplifier (Fmax=1.3GHz) PLL lock/unlock status display out put (Built-in pull up resistor ) X’tal 4MHz is used to realize 1 type of tuning steps (Division ratio 1/640) Serial data input. (3 wire bus ) Built-in Power on reset system Small package (SOP/SSOP) BAND SWITCHING OUTPUTS BS3 BS2 BS1 12 LD/ftest LD/ftest OUTPUT SUPPLY 11 VCC3 VOLTAGE 3 TUNING 10 Vtu OUTPUT 9 Vin FILTER INPUT Outline 16P2S-A (FP) 16P2Z-A (GP) APPLICATION TV, VCR tuners FUNCTION RECOMMENDED OPERATING CONDITION Supply voltage range..............................................V CC1=4.5 to 5.5V VCC2=VCC1 to 13.2V VCC3=28 to 35V Rated supply voltage...........................................................V CC1=5V VCC2=12V VCC3=33V • • • • • • • 2-modulus prescaler (1/32 and 1/33) Built-in 4MHz crystal oscillator and reference divider Programmable divider (10-bit M counter, 5-bit S counter) Tri-state phase comparator Lock detector Band switch driver Op. Amp for direct tuning 1 MITSUBISHI ICS (TV) M64893FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR BLOCK DIAGRAM CRYSTAL OSCILLATOR X in 16 ENABLE INPUT ENA 15 DATA INPUT DATA 14 CLOCK INPUT CLK 13 LD/ftest OUTPUT LD/ftest 12 SUPPLY VOLTAGE 3 VCC3 11 TUNING OUTPUT Vtu 10 FILTER INPUT Vin 9 OSC 19-BIT SHIFT REGISTER LATCH VCC1 DIVIDER 10 10-BIT M COUNTER 1/32,1/33 5 5-BIT S COUNTER 4 1/8 P.O RESET BIAS BAND DRIVER PHASE DETECTOR CHARGE PUMP LOCK DETECTOR AMP AMP 1 f in PRESCALER INPUT 2 GND 3 VCC1 SUPPLY VOLTAGE 1 4 VCC2 SUPPLY VOLTAGE 2 5 BS4 6 BS3 7 BS2 8 BS1 BAND SWITCHING OUTPUTS 2 MITSUBISHI ICS (TV) M64893FP/GP SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR DESCRIPTION OF PIN Pin No. 1 2 3 4 5 6 7 8 Symbol fin GND VCC1 VCC2 BS4 BS3 BS2 BS1 Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0V. Power supply voltage terminal. 5.0V ±0.5V Power supply for band switching, Vcc 1 to 13.2V PNP open collector method is used. When the band switching data is "H", the output is ON. When it is "L", the output is OFF. This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f 1/N) is ahead compared to the reference frequency (fref), the "source" current state becomes active. If it is behind, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35V When 19 bit data is input,lock detector is output. When 27 bit data is input, lock detector is output, the programmable freq. Divider output and reference freq. Output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable freq. divider set up. This is normally at a "L". When this is at "H", data and clock signals are received. Data is read into the latch when the 19th pulse of the clock signal falls. 4.0MHz crystal oscillator is connected. 9 Vin Filter input (Charge pump output) Tuning output Power supply voltage 3 Lock detect/Test port Clock input Data input Enable input This is connected to the crystal oscillator 10 11 12 13 14 15 16 Vtu VCC3 LD/ftest CLK DATA ENA Xin ABSOLUTE MAXIMUM RATINGS (Ta=-20°C to +75°C, unless otherwise noted) Symbol VCC1 VCC2 VCC3 VI VO VBSOFF IBSON tBSON Pd Topr Tstg Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Output voltage Voltage applied when the band output is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Conditions Pin3 Pin4 Pin11 Not to exceed VCC1 LD output Ratings 6.0 14.4 36.0 6.0 6.0 14.4 Per 1 band output circuit 50mA per 1 band output circuit 3circuit are pn at same time Ta=+75°C 50.0 10 470 -20 to +75 -40 to +125 Unit V V V V V V mA sec mW °C °C RECOMMENDED OPERATING CONDITIONS (Ta=-20°C to +75°C, unless otherwise noted) Symbol VCC1 VCC2 VCC3 fopr1 fopr2 IBDL Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Conditions Pin3 Pin4 Pin11 Crystal oscillation circuit N.


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