Document
January 14, 2003 Rev.0.7
Preliminary
Notice: This is not final specification. Some parametric limits are subject to change.
DESCRIPTION
The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5636UG operates on 2.5V power/ 1.8V I/O supply or a single 2.5V power supply and are 2.5V CMOS compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225, and 200 MHz • Fast access time: 2.6, 2.8, 3.2 ns • Single 2.5V -5% and +5% power supply VDD • Separate VDDQ for 2.5V or 1.8V I/O • Individual byte write (BWa# - BWd#) controls may be tied
LOW • Single Read/Write control pin (W#) • CKE# pin to enable clock and suspend operations • Internally self-timed, registers outputs eliminate the need
to control G# • Snooze mode (ZZ) for power down • Linear or Interleaved Burst Modes • Three chip enables for simple depth expansion • JTAG boundary scan support
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
APPLICATION
High-end networking products that require high bandwidth, such as switches and routers.
FUNCTION
Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#, BWd#) and Read/Write (W#). Write operations are controlled by the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the SRAM in the power-down state.The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV LOW input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input.
Package 165(11x15) bump BGA Body Size (13mm x 15mm) Bump Pitch 1.0mm
PART NAME TABLE
Part Name M5M5T5636UG - 25
Access 2.6ns
Cycle 4.0ns
Active Current (max.)
560mA
Standby Current (max.)
30mA
M5M5T5636UG - 22 2.8ns
4.4ns
500mA
30mA
M5M5T5636UG - 20 3.2ns
5.0ns
440mA
30mA
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Preliminary M5M5T5636UG REV.0.7
BUMP LAYOUT(TOP VIEW)
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
165bump-BGA 1 2 3 4 5 6 7 8 9 10 11
A NC A7 E1# BWc# BWb# E3# CKE# ADV A17 A8 NC
B NC A6 E2 BWd# BWa# CLK W# G# A18 A9 NC
C DQPc NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPb
D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb
H MCH MCH NC VDD VSS VSS VSS VDD NC NC ZZ
J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa
N DQPd NC VDDQ VSS
NC
NC
MCH
VSS
VDDQ
NC DQPa
P NC
NC
A5
A3
TDI
A1
TDO
A15
A13
A11
NC
R LBO# NC
A4
A2
TMS
A0
TCK
A16
A14
A12
A10
Note1. MCH means "Must Connect High". MCH should be connected to HIGH.
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Preliminary M5M5T5636UG REV.0.7
BLOCK DIAGRAM
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
VDD
VDDQ
A0 A1 A2~18
19
ADDRESS REGISTER
19 17
A1 D1
A0 D0
LINEAR/
INTERLEAVED BURST
COUNTER
A1' Q1
A0' Q0
LBO# CLK CKE#
ZZ ADV BWa# BWb# BWc# BWd# W#
G# E1# E2 E3#
WRITE ADDRESS REGISTER1
WRITE ADDRESS REGISTER2
19 19
WRITE REGISTRY AND
DATA COHERENCY CONTROL LOGIC
READ LOGIC
BYTE1 WRITE DRIVERS
BYTE2 WRITE DRIVERS
BYTE3 WRITE DRIVERS
BYTE4 WRITE DRIVERS
36
256Kx36 MEMORY
ARRAY
INPUT REGISTER1
INPUT REGISTER0
OUTPUT REGISTERS OUTPUT SELECT
OUTPUT BUFFERS
DQa DQPa DQb DQPb DQc DQPc DQd DQPd
VSS
Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter. Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
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Preliminary M5M5T5636UG REV.0.7
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
PIN FUNCTION Pin
A0~A18
BWa#, BWb#, BWc#, BWd#
CLK E1#
Name Synchronous Address Inputs
Synchronous Byte Write Enables
Clock Input
Synchronous Chip Enable
Function
These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is des.