M5M54R08J-12

MITSUBISHI LSIs M5M54R08J-12,-15 1997.11.20 Rev.F 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R08J is a family of 524288-word by 8-bit static RAMs, fabricated with the high performance CMOS silicon gate PIN CONFIGURATION (TOP VIEW) A0 A1 A2 lead package(SOJ). A3 These device operate on a single 5V supply, and are directly A4 chip select TTL compatible. They include a power down feature as well. S input data inputs/ DQ1 FEATURES outputs DQ2 Fast access time M5M54R08J-12 12ns(max) (5V) VCC M5M54R08J-15 15ns(max) (0V) GND data Low power dissipation Active 550mW(typ) DQ3 inputs/ Stand by 5mW(typ) DQ4 outputs write control W Single +5V power supply input Fully static operation : No clocks, No refresh A5 Common data I/O A6 address Easy memory expansion by S A7 inputs Three-state outputs : OR-tie capability A8 OE prevents data contention in the I/O bus A9 Directly TTL compatible : All inputs and outputs The M5M54R08J is offered in a 36-pin plastic small outline Jaddress inputs process and designed for high speed application. 1 2 3 4 5 36 35 34 33 32 6 7 8 9 10 11 12 13 14 15 16 17 18 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 address A17 inputs A16 A15 output enable OE input data DQ 8 inputs/ DQ7 outputs GND (0V) VCC (5V) DQ6 data inputs/ DQ5 outputs A14 A13 address A12 inputs A11 A10 NC M5M54R08J Outline 36P0K (SOJ) APPLICATION High-speed memory units PACKAGE 36pin 400mil SOJ BLOCK DIAGR...