Document
'97.4.7
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5255DP,FP is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface.
PIN CONFIGURATION (TOP VIEW)
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /W A13 A8 A9 A11 S2 A10 /S1 DQ8 DQ7 DQ6 DQ5 DQ4
M5M5255DP,FP
FEATURE
Type Access Power supply current time Active Stand-by (max) (max) (max) 45ns 55ns 70ns 45ns 55ns 70ns 55mA
(Vcc=5.5V)
DQ3 GND 14
M5M5255DP, FP-45LL M5M5255DP, FP-55LL M5M5255DP, FP-70LL M5M5255DP, FP-45XL M5M5255DP, FP-55XL M5M5255DP, FP-70XL
Outline 28P4 (DP) 28P2W-C (DFP) 20µA
(Vcc=5.5V)
5µA
(Vcc=5.5V)
0.05µA
(Vcc=3.0V, Typical)
•Single +5V power supply •No clocks, no refresh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •Simple memory expantion by /S1, S2 •Common Data I/O •Battery backup capability •Low stand-by current··········0.05µA(typ.)
PACKAGE
M5M255DP M5M5255DFP : 28 pin 600 mil DIP : 28 pin 450 mil SOP
APPLICATION
Small capacity memory units
MITSUBISHI ELECTRIC
1
'97.4.7
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5255DP,FP is determined by a combination of the device control inputs /S1, S2 and /W. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S1 or S2, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. A read cycle is executed by setting /W at a high level while /S1 and S2 are in an active state(/S1="L", S2="H"). When setting /S1 at a high level or S2 at a low level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by /S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
FUNCTION TABLE
/S1 S2 /W H L L L X L H H X X L H Mode Non selection Non selection Write Read DQ High-impedance High-impedance DIN DOUT Icc Stand-by Stand-by Active Active
FUNCTION TABLE
A8 A 13 A 14 A 12 A7 A6 A5 A4 ADDRESS INPUT A3
25 26 ADDRESS INPUT BUFFER ROW DECODER 1 2 2 3 4 5 6 7 32768 WORD SENSE ANPLIFIER OUTPUT BUFFER X 8BIT
11 12 13 15 16 17 18 19
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DATA I/O
(512 ROWS X 512 COLUMNS)
A2 A1 A0 A 10 A 11 A9 WRITE CONTROL INPUT /W CHIP SELECT INPUT1 /S1 CHIP SELECT S2 INPUT2
8 DATA INPUT BUFFER COLUMN DECODER 9 10 21 23 24 ADDRESS INPUT BUFFER
CLOCK GENERATOR
27 20
28 14
VCC (5V) GND (0V)
22
MITSUBISHI ELECTRIC
2
'97.4.7
MITSUBISHI LSIs
M5M5255DP,FP -45LL,-55LL,-70LL, -45XL,-55XL,-70XL
262,144-BIT (32,768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Supply voltage Vcc VI VO Pd Topr Tstg Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25°C Ratings -0.3*~7.0 -0.3*~Vcc+0.3
(Max 7.0)
Unit V V V mW
°C °C
0~Vcc 700 0~70 -65~150
* -3.0V in case of AC ( Pulse width ≤ 30ns )
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH1 VOH2 VOL II IO Parameter High-level input voltage Low-level input voltage High-level output voltage 1 High-level output voltage 2 Low-level output voltage Input current Output current in off-state Active supply current
(AC, MOS level )
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Test conditions
Limits Min 2.2 -0.3 Typ Max
Vcc +0.3
Unit V V V V
0.8
IOH=-1mA IOH=-0.1mA IOL=2mA VI=0~Vcc /S1=VIH or S2=VIL or /OE=VIH VI/O=0~Vcc 45ns /S1≤0.2V, S2>Vcc-0.2V Other inputs<0.2V or >Vcc-0.2V 55ns Output-open(duty 100%) 70ns /S1=VIL,S2=VIH other inputs=VIH or VIL Output-open(duty 100%) S2≤0.2V or /S1≥Vcc-0.2V, S2≥Vcc-0.2V other inputs=0~Vcc /S1=VIH or S2=VIL, other inputs=0~Vcc 45ns 55ns 70ns -LL -XL
2.4
Vcc -0.5
0.4 ±1 ±1 35 30 25 35 30 25 50 45 40 55 50 45 20
V uA uA
Icc1
mA
Icc2
Active supply current
(AC, TTL level )
mA
Icc3
Stand-by current
uA 5 3 mA
Icc4
Stand-by current
* -3.0V in case of AC ( Pulse width ≤ 30ns )
CAPACITANCE
Sym.