Document
MITSUBISHI MITSUBISHI LSIs LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO EDO ( HYPER ( HYPER PAGE PAGE MODE MODE ) 4194304-BIT ) 4194304-BIT ( 1048576-WORD ( 1048576-WORD BY BY 4-BIT 4-BIT ) DYNAMIC ) DYNAMIC RAM RAM
DESCRIPTION
This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated with the high performance CMOS process,and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application.
PIN CONFIGURATION (TOP VIEW)
DQ1 1 DQ2 2 W 3 RAS 4 A9 5
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE
FEATURES
A0 9 18 A8 17 A7 16 A6 15 A5 14 A4
Type name
M5M44405CXX-5,-5S M5M44405CXX-6,-6S M5M44405CXX-7,-7S
RAS CAS access access time time (max.ns) (max.ns)
Address OE Cycle Power access access time dissipatime time tion (max.ns) (max.ns) (min.ns) (typ.mW)
A1 10 A2 11 A3 12 VCC 13
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
500 400 350
XX=J,TP
Outline 26P0J (300mil SOJ)
Standard 26 pin SOJ, 26 pin TSOP(II) Single 5V±10%supply Low stand-by power dissipation CMOS lnput level 5.5mW (Max) * CMOS lnput level 550µW (Max) Low operating power dissipation M5M44405Cxx-5,-5S 687.5mW (Max) M5M44405Cxx-6,-6S 550.0mW (Max) M5M44405Cxx-7,-7S 467.5mW (Max) Self refresh capabiility * Self refresh current 120µA(max) Extended refresh capability * Extended refresh current 120µA(max) Hyper-page mode (1024-bit random access), Read-modify- write, RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR self refresh(-5S,-6S,-7S) capabilities Early-write mode and OE and W to control output buffer impedance All inputs, output TTL compatible and low capacitance 1024 refresh cycles every 16.4ms (A0~A9) 1024refresh cycle every 128ms (A0~A9) * 4-bit parallel test mode capability * : Applicable to self refresh version (M5M44405CJ,TP-5S,-6S,-7S : option) only
DQ1 1 DQ2 2 W 3 RAS 4 A9 5
26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE
A0 9 A1 10 A2 11 A3 12 VCC 13
18 A8 17 A7 16 A6 15 A5 14 A4
Outline 26P3Z-E (300mil TSOP)
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT, Frame Buffer memory for CRT
PIN DESCRIPTION
Pin name A0~A9 DQ1~DQ4 RAS CAS W OE Vcc Vss Function Address Inputs Data Inputs / Outputs Row Address Strobe Input Column Address Strobe Input Write Control Input Output Enable Input Power Supply (+5V) Ground (0V)
1
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
FUNCTION
The M5M44405CJ, TP provide, in addition to normal read, write, and read-modify-write operations,a number of other functions, e.g., hyper page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation Read Write (Early write) Write (Delayed write) Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Self refresh * Stand-by Inputs RAS ACT ACT ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT ACT NAC ACT ACT ACT DNC W NAC ACT ACT ACT DNC DNC NAC NAC DNC OE ACT DNC NAC ACT DNC ACT DNC DNC DNC
Row address Column address
APD APD APD APD APD DNC DNC DNC DNC
APD APD APD APD DNC DNC DNC DNC DNC
Input/Output Output Input OPN VLD APD OPN APD IVD APD VLD DNC OPN OPN VLD DNC OPN DNC OPN DNC OPN
Refresh Remark YES YES YES YES YES YES YES YES NO
HyperPage mode identical
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : invalid, APD : applied, OPN : open
BLOCK DIAGRAM
COLUMN ADDRESS STROBE INPUT CAS ROW ADDRESS RAS STROBE INPUT WRITE CONTROL INPUT W A0~A9
VCC (5V) CLOCK GENERATOR CIRCUIT VSS (0V)
COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
(4) DATA IN BUFFERS DQ1
SENSE REFRESH AMPLIFER & I /O CONTROL
DQ2 DQ3 DQ4 (4) DATA OUT BUFFERS
DATA INPUTS / OUTPUTS
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
ROW A0~ A9 DECODER
MEMORY CELL (4,194,304 BITS)
OE OUTPUT ENABLE INPUT
M5M44405CJ,TP-5,-5S:Under development
MITSUBISHI LSIs
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ratings -1~7 -1~7 -1~7 50 1000 0~70 -65~150 Unit V V V mA mW ˚C ˚C
Ta=25˚C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70˚C, unless otherwise noted) (Note 1)
Symbol VCC VSS VIH VIL Supply voltage Supply voltage High-level input voltage, all inputs DQ1~4 Low-level input voltage others Parameter Limits Min 4.