M5M417400CTP-7S

MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM DESCRIPTION This is a family of 4194304-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process, and is ideal for large-capacity memory systems where high speed, low power dissipation, and low costs are essential. The use of double-layer metal process combined with twin-well CMOS technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. PIN DESCRIPTION Pin name A0 ~ A11 DQ1 ~ DQ4 RAS CAS W OE VCC VSS Function Address inputs Data inputs / outputs Row address strobe input Column address strobe input Write control input Output enable input Power supply (+5V) Ground (0V) PIN CONFIGURATION (TOP VIEW) FEATURES RAS CAS access time (max.ns) Address access time (max.ns) OE access time (max.ns) Cycle time (min.ns) Power dissipation (typ.mW) Type Name access time (max.ns) M5M417400CXX-5,-5S M5M417400CXX-6,-6S M5M417400CXX-7,-7S 50 60 70 13 15 20 25 30 35 13 15 20 90 110 130 655 540 475 XX=J, TP Standard 26 pin SOJ, 26 pin TSOP Single 5V ± 10% supply Low stand-by power dissipation 5.5mW(Max) ..................................CMOS Input level 2.2mW (Max)* ...............................CMOS Input level Low operating power dissipation M5M417400Cxx-5,-5S .................... 80...