M59MR032D

M59MR032C M59MR032D 32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory s SUPPLY VOLTAGE – VDD = VDDQ = 1.65V to 2.0V for Program, Erase and Read s s – VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ – Configurable Burst mode Read – Page mode Read (4 Words Page) – Random Access: 100ns LFBGA54 (ZC) 10 x 4 ball array µBGA46 (GC) 10 x 4 ball array BGA µBGA s PROGRAMMING TIME – 10µs by Word typical – Double Word Programming Option s MEMORY BLOCKS – Dual Bank Memory Array: 8 Mbit - 24 Mbit – Parameter Blocks (Top or Bottom location) Figure 1. Logic Diagram s DUAL BANK OPERATIONS – Read within one Bank while Program or Erase within the other – No delay between Read and Write operations VDD VDDQ VPP 5 A16-A20 W E G RP WP L K M59MR032C M59MR032D BINV WAIT 16 ADQ0-ADQ15 s BLOCK PROTECTION/UNPROTECTION – All Blocks protected at Power-up – Any combination of Blocks can be protected s s s s COMMON FLASH INTERFACE (CFI) 64 bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M59MR032C: A4h – Bottom Device Code, M59MR032D: A5h s VSS AI90109 April 2001 1/49 M59MR032C, M59MR032D Figure 2. LFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 9 10 A DU DU B DU DU C DU DU D DU DU E WAIT VSS K VDD W VPP A19 A17 F VDDQ A16 A20 L BINV RP WP A18 E VSS G VSS ADQ7 A...