Document
M58CR064C, M58CR064D M58CR064P, M58CR064Q
64 Mbit (4Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory
FEATURES SUMMARY s SUPPLY VOLTAGE – VDD = 1.65V to 2V for Program, Erase and Read – VDDQ = 1.65V to 3.3V for I/O Buffers – VPP = 12V for fast Program (optional)
s
Figure 1. Package
SYNCHRONOUS / ASYNCHRONOUS READ – Synchronous Burst Read mode : 54MHz – Asynchronous/ Synchronous Page Read mode – Random Access: 85, 90, 100, 120ns
FBGA
s
PROGRAMMING TIME – 10µs by Word typical – Double/Quadruple Word Program option
TFBGA56 (ZB) 6.5 x 10mm
s
MEMORY BLOCKS – Dual Bank Memory Array: 16/48 Mbit – Parameter Blocks (Top or Bottom location)
s
DUAL OPERATIONS – Program Erase in one Bank while Read in other – No delay between Read and Write operations
s
ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M58CR064C: 88CAh – Bottom Device Code, M58CR064D: 88CBh – Top Device Code, M58CR064P: 8801h – Bottom Device Code, M58CR064Q: 8802h
s
BLOCK LOCKING – All blocks locked at Power up – Any combination of blocks can be locked – WP for Block Lock-Down
s
SECURITY – 128 bit user programmable OTP cells – 64 bit unique device number – One parameter block permanently lockable
s s
COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK
June 2003
1/70
M58CR064C, M58CR064D, M58CR064P, M58CR064Q
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .