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M58CR032C Dataheets PDF



Part Number M58CR032C
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description 32 Mbit 2Mb x 16 / Dual Bank / Burst 1.8V Supply Flash Memory
Datasheet M58CR032C DatasheetM58CR032C Datasheet (PDF)

M58CR032C M58CR032D 32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory PRELIMINARY DATA FEATURES SUMMARY s SUPPLY VOLTAGE – VDD = 1.65V to 2V for Program, Erase and Read – VDDQ = 1.65V to 3.3V for I/O Buffers s Figure 1. Packages – VPP = 12V for fast Program (optional) SYNCHRONOUS / ASYNCHRONOUS READ – Burst mode Read: 54MHz – Page mode Read (4 Words Page) – Random Access: 85, 100, 120 ns FBGA s PROGRAMMING TIME – 10µs by Word typical – Double/Quadruple Word programming option T.

  M58CR032C   M58CR032C


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M58CR032C M58CR032D 32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory PRELIMINARY DATA FEATURES SUMMARY s SUPPLY VOLTAGE – VDD = 1.65V to 2V for Program, Erase and Read – VDDQ = 1.65V to 3.3V for I/O Buffers s Figure 1. Packages – VPP = 12V for fast Program (optional) SYNCHRONOUS / ASYNCHRONOUS READ – Burst mode Read: 54MHz – Page mode Read (4 Words Page) – Random Access: 85, 100, 120 ns FBGA s PROGRAMMING TIME – 10µs by Word typical – Double/Quadruple Word programming option TFBGA56 (ZB) 6.5 x 10 mm s MEMORY BLOCKS – Dual Bank Memory Array: 8/24 Mbit – Parameter Blocks (Top or Bottom location) s DUAL OPERATIONS – Read in one Bank while Program or Erase in other – No delay between Read and Write operations s ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M58CR032C: 88C8h – Bottom Device Code, M58CR032D: 88C9h s BLOCK LOCKING – All blocks locked at Power up – Any combination of blocks can be locked – WP for Block Lock-Down s SECURITY – 64 bit user programmable OTP cells – 64 bit unique device identifier – One parameter block permanently lockable s s COMMON FLASH INTERFACE (CFI) 100,000 PROGRAM/ERASE CYCLES per BLOCK September 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/63 M58CR032C, M58CR032D TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD Supply Voltage (1.65V to 2V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage (1.65V to 3.3V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VPP Program Supply Voltage (12V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS and V SSQ Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Asynchronous Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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