MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS P−channel and N−channel en...
MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS P−channel and N−channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.
Features
Buffered Data Inputs Common Clock Clock Polarity Control Q and Q Outputs Double Diode Input Protection Supply Voltage Range = 3.0 Vdc to 1 8 Vdc Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range (DC or Transient)
−0.5 to +18.0 −0.5 to VDD + 0.5
V V
Iin, Iout
Input or Output Current (DC or Transient) per Pin
±10 mA
PD Power Dissipation, per Package (Note 1)
...