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MC10E160, MC100E160 5V ECL 12-Bit Parity Generator/Checker
The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS
1 28
• • • • • • • •
Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 900 ps Max. D to Q/Q Output Enable Asynchronous Register Reset Dual Clocks PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input to 50 KW Pulldown Resistors Machine Model; > 7 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
PLCC−28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week
MC10E160FN AWLYYWW
1 28
• • ESD Protection: Human Body Model; > 1 KV, • • Moisture Sensitivity Level 1 • •
MC100E160FN AWLYYWW
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 312 devices
ORDERING INFORMATION
Device MC10E160FN MC10E160FNR2 MC100E160FN MC100E160FNR2 Package PLCC−28 PLCC−28 PLCC−28 PLCC−28 Shipping † 37 Units/Rail 500 Units/Reel 37 Units/Rail 500 Units/Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
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Publication Order Number: MC10E160/D
MC10E160, MC100E160
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D4 25 D5 D6 D7 VEE D8 D9 D10 26 27 28
1
D3 24
D2 23
D1 22
D0 21
EN VCCO 20 19 18 17 16 Q Q VCC Y Y VCCO NC
PIN DESCRIPTION
PIN D0 − D11 S-IN EN HOLD SHIFT CLK1, CLK2 R Q, Q Y, Y VCC, VCCO VEE NC FUNCTION ECL Data Inputs ECL Serial Data Input ECL Enable, active LOW ECL Hold, active LOW ECL Shift, active HIGH ECL Clock Inputs ECL Reset Inputs ECL Direct Output ECL Register Output Positive Supply Negative Supply No Connect
Pinout: 28-Lead PLCC (Top View)
15 14 13 12
2 3 4 5 6 7 8 9 10 11
D11 HOLD S-IN SHIFT CLK1 CLK2 R * All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 EN HOLD S-IN SHIFT CLK1 CLK2 R
LOGIC DIAGRAM
Q
0 MUX 1 SEL
0 MUX 1 SEL
D R
Y Y
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MC10E160, MC100E160
MAXIMUM RATINGS (Note 1)
Symbol VCC VI Iout TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Wave Solder 0 LFPM 500 LFPM Standard Board <2 to 3 sec @ 248°C 28 PLCC 28 PLCC 28 PLCC Condition 1 VEE = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2.