MC10195FN

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex Inverter/Buffer The MC10195 is a Hex Buffer Inverter which is built using six EXCLUSIVE NOR gates. There is a common input to these gates which when placed low or left open allows them to act as inverters. With the common input connected to a high logic level the MC10195 is a hex buffer, useful for high fanout clock driving and reducing stub lengths on long bus lines. MC10195 PD = 200 mW typ/pkg (No Load) tpd = 2.8 ns typ (B–Q) tpd = 3.8 ns typ (A–Q) tr, tf = 2.5 ns typ (20%–80%) L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 LOGIC DIAGRAM 9 5 A B Q 2 6 3 DIP PIN ASSIGNMENT VCC1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q6 Q5 Q4 B6 B5 B4 A 7 4 Q1 Q2 Q3 10 13 B1 B2 B3 11 14 VEE 12 15 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–36 of the Motorola MECL Data Book (DL122/D). TRUTH TABLE Inputs A L L H H B L H L H Output Q H L L H 3/93 © Motorola, Inc. 1996 3–164 REV 5 MC10195 ELECTRICAL CHARACTERISTICS Test Limits Pin Pi Under Test 8 5 9 5 2 2 2 2 0.5 –1.060 –1.890 –1.080 –1.655 –0.890 –1.675 –30°C Min Max 54 425 460 0.5 –0.960 –1.850 –0.980 –1.630 –0.810 –1.650 Min +25°C Typ 39 Max 49 265 290 0.3 –0.890 –1.825 –0.910 –1.595 –0.700 –1.615 Min +85°C Max 54 265 290 Unit mAdc µAdc µAdc Vdc Vdc Vdc Vdc ns t5+2– t7–4+ t10+13+ t11–14– t9–14– t2+ t2– 2 4 13 14 14 ...