MC10162

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Binary to 1-8 Decoder (High) The MC10162 is designed to convert three lines of input data to a one–of–eight output. The selected output will be high while all other outputs are low. The enable inputs, when either or both are high, force all outputs low. The MC10162 is a true parallel decoder. No series gating is used internally, eliminating unequal delay times found in other decoders. This device is ideally suited for demultiplexer applications. One of the two enable inputs is used as the data input, while the other is used as a data enable input. A complete mux/demux operation on 16 bits for data distribution is illustrated in Figure 1 of the MC10161 data sheet. PD = 315 ns typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ (20%–80%) MC10162 L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02 LOGIC DIAGRAM E0 2 E1 15 6 Q0 5 Q1 4 Q2 A 7 3 Q3 13 Q4 B 9 12 Q5 11 Q6 C 14 10 Q7 DIP PIN ASSIGNMENT VCC1 E0 Q3 Q2 Q1 Q0 A VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 E1 C Q4 Q5 Q6 Q7 B VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 TRUTH TABLE INPUTS E0 L L L L L L L L H X E1 L L L L L L L L X H C L L L L H H H H X X B L L H H L L H H X X A L H L H L H L H X X Q0 H L L L L L L L L L Q1 L H L L L L L L L L Q2 L L H L L L L L L L OUTPUTS Q3 L L L H L L L L L L Q4 L L L L H L L L L L Q5 L L L L L H L L L L Q6 L L L L L L H L L L Q7 L L L L L L L H L L Pin assignment is for Dual–in–Line Package....