MC10133

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad Latch The MC10133 is a high speed, low power, quad latch consisting of four bistable latch circuits with D type inputs and gated Q outputs, allowing direct wiring to a bus. When the clock is high, outputs will follow D inputs. Information is latched on the negative going transition of the clock. The outputs are gated when the output enable (G) is low. All four latches may be clocked at one time with the common clock (CC), or each half may be clocked separately with its clock enable (CE). MC10133 PD = 310 mW typ/pkg (No Load) tpd = 4.0 ns typ tr, tf = 2.0 ns typ (20%–80%) L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 LOGIC DIAGRAM D0 3 Q0 2 Q0 G0 D1 CE 5 7 4 DIP PIN ASSIGNMENT 6 Q1 VCC1 Q0 D0 Q2 11 Q2 CE G0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q3 D3 CC CE Q2 G1 D2 Q1 CC 13 CE 12 D2 9 G1 10 D3 14 Q3 15 Q3 Q1 D1 TRUTH TABLE G H L L L C X L H H D X X L H Qn+1 L Qn L H VEE VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 C = CC + CE 9/96 © Motorola, Inc. 1996 3–13 REV 6 MC10133 ELECTRICAL CHARACTERISTICS Test Limits Pin Pi Under Test 8 3 4 5 13 3 2 2 2 2 2 2 2 2 2[ 2] 2] 2 2 2 2 2 2[ 2] 2] 0.5 –1.060 –1.060 –1.890 –1.890 –1.890 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 –1.080 –1.655 –1.655 –1.655 –1.655 –1.655 –1.655 –0.890 –0.890 –1.675 –1.675 –1.675 –30°C Min Max 82 390 425 560 560 0.5 –0.960 –0.960 –1.850 –1.850 –1.850 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –0.980 –1.630 –...