Document
MC10117 Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate
T h e M C 1 0 11 7 i s a d u a l 2 – w i d e 2 – 3 – i n p u t OR–AND/OR–AND–Invert gate. This general purpose logic element is designed for use in data control, such as digital multiplexing or data distribution. Pin 9 is common to both gates. • PD = 100 mW typ/pkg (No Load) • tpd = 2.3 ns typ • tr, tf = 2.2 ns typ (20%–80%)
LOGIC DIAGRAM
4 5 6 7 9 10 11 12 13 14 15 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8
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16 CDIP–16 L SUFFIX CASE 620 1 MC10117L AWLYYWW
3 2 PDIP–16 P SUFFIX CASE 648
16 MC10117P AWLYYWW 1 1 PLCC–20 FN SUFFIX CASE 775 10117 AWLYYWW
DIP PIN ASSIGNMENT
VCC1 AOUT AOUT A1IN A1IN A2IN A2IN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 BOUT BOUT B1IN B1IN B2IN B2IN A2IN, B2IN MC10117P
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC10117L Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
MC10117FN
Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
© Semiconductor Components Industries, LLC, 2002
1
January, 2002 – Rev. 7
Publication Order Number: MC10117/D
MC10117
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 6 9 4 4 2 3 2 3 2 3 2 3 0.5 –1.060 –1.060 –1.890 –1.890 –1.080 –1.080 –1.655 –1.655 –0.890 –0.780 –1.675 –1.675 –30°C Min Max 29 425 560 390 0.5 –0.960 –0.960 –1.850 –1.850 –0.980 –0.980 –1.630 –1.630 –0.810 –0.700 –1.650 –1.650 Min +25°C Typ 20 Max 26 265 350 245 0.3 –0.890 –0.890 –1.825 –1.825 –0.910 –0.910 –1.595 –1.595 –0.700 –0.590 –1.615 –1.615 Min +85°C Max 29 265 350 245 Unit mAdc µAdc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH*
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLA
µAdc Vdc Vdc Vdc Vdc ns
Switching Times (50Ω Load) Propagation Delay t4+2+ t4–2– t4+3– t4–3+ t2+ t3+ t2– t3– 2 2 3 3 2 3 2 3 1.4 1.4 1.4 1.4 0.9 0.9 0.9 0.9 3.9 3.9 3.9 3.9 4.1 4.1 4.1 4.1 1.4 1.4 1.4 1.4 1.1 1.1 1.1 1.1 2.3 2.3 2.3 2.3 2.2 2.2 2.2 2.2 3.4 3.4 3.4 3.4 4.0 4.0 4.0 4.0 1.4 1.4 1.4 1.4 1.1 1.1 1.1 1.1 3.8 3.8 3.8 3.8 4.6 4.6 4.6 4.6
Rise Time Fall Time
(20 to 80%) (20 to 80%)
* Inputs 4, 5, 12 and 13 have same IinH limit. Inputs 6, 7, 10 and 11 have same IinH limit.
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MC10117
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature –30°C +25°C +85°C Pin Under Test 8 6 9 4 4 2 3 2 3 2 3 2 3 4, 9 4 9 4 9 VIHmax –0.890 –0.810 –0.700 VILmin –1.890 –1.850 –1.825 VIHAmin –1.205 –1.105 –1.035 VILAmax –1.500 –1.475 –1.440 VEE –5.2 –5.2 –5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 4 4 4 9 +1.11V 4 Pulse In 4 4 4 4 4 4 4 4 Pulse Out 2 2 3 3 2 3 2 3 8 8 8 8 –3.2 V 8 8 8 8 8 8 8 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH*
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Propagation Delay Logic 1 Logic 0 Logic 1 Logic 0 (50Ω Load) t4+2+ t4–2– t4+3– t4–3+ (20 to 80%) (20 to 80%) t2+ t3+ t2– t3– VOH VOL VOHA VOLA
4, 9 9
2 2 3 3 2 3 2 3
9 9 9 9 9 9 9 9
Rise Time Fall Time
* Inputs 4, 5, 12 and 13 have same IinH limit. Inputs 6, 7, 10 and 11 have same IinH limit. Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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3
MC10117
PACKAGE DIMENSIONS
PLCC–20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C
B –N– Y BRK D –L– –M– W D X V A Z R 0.007 (0.180) 0.007 (0.180)
M
0.007 (0.180) U
M
T L-M
M
S
N
S S
0.007 (0.180)
T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D–D T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
K1 K
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J –T–
SEATING PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF .