Translator
MC100LVELT22
Translator, Dual LVTTL / LVCMOS to Differential LVPECL
Description The MC100LVELT22 is a dual LVTTL/LVCMOS...
Description
MC100LVELT22
Translator, Dual LVTTL / LVCMOS to Differential LVPECL
Description The MC100LVELT22 is a dual LVTTL/LVCMOS to differential
LVPECL translator. Due to LVPECL (Low Voltage Positive ECL) levels, only +3.3V and ground is required. The small 8−lead package outline with low skew dual gate design makes the MC100LVELT22 ideal for applications which require translation of a clock and/or data signal.
Features
350 ps Typical Propagation Delay <100 ps Output−to−Output Skew Flow Through Pinouts The 100 Series Contains Temperature Compensation LVPECL Operating Range: VCC = 3.15 V to 3.45 V
with GND = 0 V
When Unused TTL Input is left Open, Q Output will Default High These are Pb−Free Devices
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8
1 SOIC−8 D SUFFIX CASE 751
MARKING DIAGRAMS*
8
KVT22 ALYW
G 1
8
1
TSSOP−8 DT SUFFIX CASE 948R
8
KR22 ALYWG
G 1
A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
July, 2016 − Rev. 12
Publication Order Number: MC100LVELT22/D
Q0 1
Q0 2 LVPECL
Q1 3
MC100LVELT22
8 VCC
7 D0 LVTTL/ LVCMOS
6 D1
Table 1. PIN DESCRIPTION
PIN
Qn, Qn D0, D1 VCC GND
FUNCTION
LVPECL Differential Outputs LVTTL/LVCMOS Inputs Positive Supp...
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