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MC100LVEL12 3.3V ECL Low Impedance Driver
Description
The MC100LVEL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is functionally equivalent to the EL12 device and operates from a 3.3 V power supply. With propagation delays equivalent to the EL12, the LVEL12 is ideally suited for those applications which require the ultimate in AC performance in a low voltage environment.
Features
http://onsemi.com MARKING DIAGRAMS*
8 1 SOIC−8 D SUFFIX CASE 751 8 1 TSSOP−8 DT SUFFIX CASE 948R 8 KVL12 ALYW G 1
• 445 ps Propagation Delay • Dual Outputs for 25 W Drive Applications • ESD Protection: >4 kV Human Body Model,
> 200 V Machine Model
8 KV12 ALYWG G
• The 100 Series Contains Temperature Compensation • PECL Mode Operating Range:VCC = 3.0 V to 3.8 V • • • • • • • •
with VEE = 0 V NECL Mode Operating Range: VCC= 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors www.DataSheet4U.com Q Output will Default LOW with All Inputs Open or at VEE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D Flammability Rating: UL−94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 83 devices Pb−Free Packages are Available
1
1 DFN8 MN SUFFIX CASE 506AA
A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 3
1
Publication Order Number: MC100LVEL12/D
4A M G G 4
MC100LVEL12
Table 1. PIN DESCRIPTION
Qa 1 8 VCC PIN D0, D1 Qa, Qa; Qb, Qb VCC VEE EP FUNCTION ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply Exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply or leave floating open.
Qb
2
7
D0
Qa
3
6
D1
Qb
4
5
VEE
Figure 1. Logic Diagram and Pinout Assignment
Table 2. MAXIMUM RATINGS
Symbol VCC VEE VI Iout TA Tstg qJA qJC qJA qJC qJA Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Thermal Resistance (Junction−to−Ambient) Thermal Resistance (Junction−to−Case) Thermal Resistance (Junction−to−Ambient) Wave Solder Pb Pb−Free 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm Standard Board 0 lfpm 500 lfpm <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP DFN8 DFN8 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to .