MC100EPT26

MC100EPT26 3.3 V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8-lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. The VBB output allows the EPT26 to be used in a Single-Ended input mode. In this mode the VBB output is tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. If used, the VBB pin should be bypassed to ground with > 0.01ĂmF capacitor. For a Single-Ended direct connection, use an external voltage reference source such as a resistor divider. Do not use VBB for a Single-Ended direct connection or port to another device. Features 1.4 ns Typical Propagation Delay Maximum Frequency = > 275 MHz Typical The 100 Series Contains Temperature Compensation Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V 24 mA TTL outputs Q Outputs Will Default LOW with Inputs Open or at VEE VBB Output These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.com 8 1 8 1 SOIC−8 NB TSSOP−8 DFN8 D SUFFIX DT SUFFIX MN SUFFIX CASE 751−07 CASE 948R−02 CASE 506AA MARKING DIAGRAMS* 8 KPT26 ALYW G 1 SOIC−8 NB 8 KA26 ALYWG G 1 TSSOP−8 1 3W MG 4G DFN8 A = Assembly Location L = Wafer Lot Y = Year W = Wor...