MC100E336

MC10E336, MC100E336 5VĄECL 3ĆBit Registered Bus Transceiver The MC10E/MC100E336 contains three bus transceivers with both transmit and receive registers. The bus outputs (BUS0–BUS2) are specified for driving a 25 Ω bus; the receive outputs (Q0 – Q2) are specified for 50 Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level — when LOW, the outputs go to –2.0 V and the output emitter-follower is “off”, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors. The Transmit Enable pins (TEN) control whether current data is held in the transmit register, or new data is loaded from the A/B inputs. A LOW on both of the Bus Enable inputs (BUSEN), when clocked through the register, disables the bus outputs to –2.0 V. The receiver section clocks bus data into the receive registers, after gating with the Receive Enable (RXEN) input. All registers are clocked by a positive transition of CLK1 or CLK2 (or both). Additio...